邏輯器件 的英文怎麼說

中文拼音 [luóqìjiàn]
邏輯器件 英文
logic device
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 件 : Ⅰ量詞（用於個體事物） piece; article; item Ⅱ名詞1. （指可以一一計算的事物） 2. （文件） letter; correspondence; paper; document
  • 邏輯 : logic
  1. There are two effective schemes to realize the interface conveniently at present : one is to adopt cpld or fpga and the other is to adhibit special interface chip

    目前實現pci介面的有效方案有兩種：採用可編程邏輯器件cpld或fpga和採用專用介面晶元。
  2. The circuits driving the ccd and processing the video signal are implemented by means of cpld ( complex programmable logic device ) and hdl ( hardvvare description language ). the solution to solve the problem of multi - level logical competitive risks that occur in cpld circuits frequently was provided in details in the thesis

    Ccd的驅動電路和視頻信號處理電路採用cpld （可編程邏輯器件）和hdl （硬體描述語言）實現，文章對cpld電路中容易出現的多級邏輯冒險競爭情況作了專門的敘述和提出相應的解決方法。
  3. The system comprises three modules : the first is the ccd driver module, which controlled with cpld. programming the cpld to produce ccd driving pulses and synchronized communication signals. after preprocessing, the output video signals are transmitted into high resolution adc module, in which they are converted into digital signals, and then processed in arm processing module

    整個系統分為三個模塊: ccd驅動模塊的核心是一片復雜可編程邏輯器件（ cpld ） ，對其編程產生ccd的驅動脈沖及同步控制信號;視頻輸出信號經預處理后，由高精度ad轉換模塊進行采樣，將ccd輸出的模擬信號轉換成數字量;最後，將數據送入arm處理系統中進行后續處理。
  4. For logic devices, the incremental current gain is very important.

    對于邏輯器件來說，提高電流增益是非常重要的。
  5. In this paper, based on the study of vga graphic displaying theory and the theory of synchronizing display between led large - screen display system and crt image, a method, bit plane addressing method which has good effect -. high ratio of performance to price and can be implemented easily in circuits is discussed. and the principle and the implementation of the multi - gray led display system with programmable logic devices cpld and fpga are analyzed in detail

    本文在分析vga圖象顯示原理和led大屏幕與crt視頻圖像同步顯示原理的基礎上，論述了一種顯示效果較好、性能價格比高、電路上易於實現的方法? ?位平面尋址法實現多灰度圖象，並詳細分析了應用復雜可編程邏輯器件cpld和在線可編程邏輯器件fpga實現多灰度彩色led大屏幕圖像顯示的原理及電路實現。
  6. Abstract : it is an efficient method that realizing the contro l circuit of a power source system with fplds ( field programmable logic devices )

    文摘:使用現場可編程邏輯器件實現各種電源控制電路是一種非常有效的設計方法。
  7. It is an important character that using hdl describes function and behavior of logic device or system hardware

    使用硬體設計語言來描述邏輯器件及系統硬體的功能和行為是硬體描述語言編程設計方法的一個重要特徵。
  8. It implements filter groups design, wide range linear automatic gain control design, and the programmed logic device design based on vhdl, and discuss their application in initial radar system in details

    其中包括分段濾波器的設計技術，寬線性自動增益控制agc電路的設計技術，以及基於vhdl語言的可編程邏輯器件的設計技術，並對其在數據採集系統中的應用作了詳細的討論。
  9. The designing process of the edac circuit is described in the paper. the time simulation is analysed, too. the designment of the circuit has access the hardware debug, and can woks normally

    此外還將第一輪設計中的基本邏輯器件如與、或、非門以及諸如244 、 255 、譯碼器等小規模元器件都集成到fpga內部來實現。
  10. Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises

    3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。
  11. Gps is a planet wireless conductance system which is global and all - weather, gps can offer high precision time orientation information to infinite user, clock precision reachs 10 ? 6 magnitude 。 not only changes traditional time method of quartz crystal clock, but also replaces wireless shortwave and even more lowfrequency signal and tv signal whose overlay range is limited and low precision, offers advantage to geology field task, achieve automatization and high precision of seismic flow observation

    利用gps授時信號全方位、全天候、連續性、實時性和高精度的特點，以gps信號為基準來校準本地時鐘（晶體振蕩時鐘或原子鐘） ，將gps接收機輸出信號的長期穩定度和恆溫晶振的短期穩定度相結合，應用大規模可編程邏輯器件，設計和實現了由pc104控制的實時在線授時系統。
  12. Implementation of programmable logic device in timing control circuit

    定時控制電器的可編程邏輯器件的實現
  13. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  14. In addition, the interface problem and the logic relative of the superior processor are solved by using a cpld

    此外，使用可編程邏輯器件（ cpld ）實現介面電路功能及系統的邏輯關系實現。
  15. According to the requirements of static compensator ( statcom ) to triggering pulse generator, an autonomous triggering system for statcom was developed based on complex programmable logic device ( cpld )

    針對靜止無功補償器（ statcom ）對觸發脈沖發生電路的要求，利用復雜可編程邏輯器件（ cpld ）開發了一種自治型statcom觸發系統。
  16. In the design, we make use of two eda tools max + plus ii and protel99. because of the using of complex programmable logical device ( cpld ), we can keep untuched the original hard circuit in design and realization of counting card, so it inherited the advantage of its predecessor. in order to quantitatively analyze the performance of data acquisition system with fifo cache, we introduced the queueing theory to build mathematic model to test its quality

    在設計中藉助了max + plusii和protel99兩個eda設計軟體。由於採用了復雜可編程邏輯器件cpld ，使得在計數卡的設計和實現中不用更改原硬體電路，對原設計的優點有很好的繼承。在驗證系統改進性能時，引入排隊論建立了數學模型對系統的工作性能進行定量分析，證明其達到了設計要求。
  17. Application of programmable logic device in circuit design of competitive answer machines

    可編程邏輯器件在搶答器電路設計中的應用
  18. As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost

    所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。
  19. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  20. As the kernel of the gsm protocol, rr is the part that distinguishes gsm from other wireless protocols. it influences the design of logical circuit

    無線資源管理層是協議棧的核心，它是區別其他無線通信協議的具體體現，它決定了物理邏輯器件的設計。
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