邏輯噪聲 的英文怎麼說
中文拼音 [luózàoshēng]
邏輯噪聲
英文
logic noise-
Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises
3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。The thesis analyses the problems on the noise of apd photoelectric receiving system. author designs apd laser signal receiving system circuits, front amplify circuit, controlling time - series logic circuits, dc / dc transform circuits. and takes apd bias voltage fuzzy control
分析了apd光電接收系統的噪聲問題，並對apd激光信號接收系統電路、前置放大電路、控制時序邏輯電路、 dc / dc變換電路進行了設計，採取了apd偏壓模糊控制。Experiment results show that this algorithm can identify static crosstalk that destroy circuits function and provide accurate information for ic back - end optimization
實驗表明，通過驗證噪聲幅值和寬度指標，演算法準確地識別出對電路邏輯功能產生影響的靜態串擾噪聲，為ic設計的後端優化提供了準確信息。Traditional static crosstalk identification methods identify crosstalk targets only using coupling capacitance and noise amplitude information, which lead to the pessimistic results and induce a long time to ic design convergence
摘要傳統的靜態串擾噪聲識別演算法只驗證耦合電容和噪聲幅值信息，沒有考慮噪聲寬度對電路邏輯功能的影響，所以給出的結果過于保守，導致設計收斂的時間被延長。Also from waveform polynomials of sequential circuits, a precise clocking method based on multiple - period sensitization is presented. a novel noise estimation method based on boolean process is first presented in this paper, using transition numbers to describe noise effects. then combined with the selection method of long sensitization paths based on waveform sensitization, a test generation approach that could generate the noisiest sensitization waveforms for long sensitizatizable paths is presented
為了適應超深亞微米電路測試的要求，本文建立了一種新的基於布爾過哈爾濱工程大學博士學位論文程論的邏輯級噪聲預測模型，用波形多項式描述的同時發生的跳變數來預測l卜足聲大小，並生成能產生最大跳變數目的輸入波形;然後同基於波形敏化的長敏化通路選擇法相結合，形成一種能產生最大噪聲效應的敏化測試波形生成新方法。A algorithm is presented to identify dynamic crosstalk noise. in the course of dynamic crosstalk noise identification, hybrid timing analysis is used to provide accurate signal arrival time, which can provide more accurate timing information than static timing analysis. at the same time, a novel test generation is chosen to verify the correlation of signals. so dynamic crosstalk noise can be identified by these accurate timing and logic information
提出了動態串擾噪聲的識別演算法.針對基於傳統靜態時序分析的結果過于保守的缺點，本演算法引入了混合時序分析，縮小了時間窗區間，為動態串擾噪聲的識別提供了準確的時序信息，與此同時，通過測試生成來驗證信號間的邏輯關系，根據這些準確的時序及邏輯信息，識別出動態串擾噪聲The thesis aims to give a scheme of designing a 48 - channel collected seismic recorder based on pci bus, and a testing machine has been completed in the basis of the scheme. pci bus provides a high data transfer speed, which solve the problem of transfering a mass of data in a short period of time ; moreover, two assistant channels are provided to sample reference signal ; the function of data correlation in real - time is also provied in the software of the instrumental system
論文論述了pci總線功能介面的實現和數據採集模塊的設計，給出了利用pci9054介面晶元設計pci介面的詳細過程，並利用driverstudio為pci數據採集系統編寫了設備驅動程序;在數據採集模塊的設計中，主要完成的工作有多通道數據採集、浮點放大以及系統的低噪聲設計，並利用cpld設計了整個系統的時序邏輯。Binary logic circuitry, on the other hand, has only two states, logic 0 and logic 1, and noire immunity of hundreds or thousands of millvolts
另一方面，二進制邏輯電路只有兩個穩態? ?邏輯0和邏輯1 ，其噪聲容限可以達到數百至數千毫伏。In order to make full behavior simulation of sigma - delta modulator, the noise models have been set, taking into account most of the sigma - delta modulator ’ s non - idealities and the final result supports the noise models. last, the main circuits of modulator have been designed, such as operational amplifier, comparator and clock generator, the design principle of noise - killed logic circuit has been presented. these circuits have been simulated
調制器的噪聲模型，考慮了影響調制器性能的一些主要非理想因素，通過模擬驗證了噪聲模型的正確性;最後，設計實現了結構中的主要電路，如運放、比較器、時鐘產生電路，闡述了噪聲抵消邏輯電路的工作原理，利用hspice和cadencespectre對各電路進行了模擬，驗證其功能。This thesis designs automobile braking performance inspecting and control system. this thesis consists of three main parts. something about automobile braking system design has been discussed in the first part according to the main requirement of gb7258 - 2004 《 the requirement for motor vehicle, running safely 》. the hardware has been designed according to the characteristic of the parameter afer establish the whole plan for inspecting it. and then working principle of each part has been introduced. and at last, we designed software depending on the require to inspection and function. we can educe the braking power of both wheels, braking moment retardarce power and other parameters. we designed sensor signal processing circuit which including power sensor signal processing circuit and speed signal measure circuit according to the require of designing parameter. ad620 is used as power sensor. in order to measure the power of the automobile braking and protect the electromotor. so we must measure both
由汽車制動測試原理以及制動性參量檢測的技術指標可知，檢測數據準確性、控制可靠性、實時性和抗干擾能力是系統設計的關鍵。本文在掌握汽車性能檢測系統結構和原理的基礎上，根據國家有關標準和汽車制動性檢測系統的控制邏輯提出了採用單片機為控制器的總體方案，設計了各部分硬體電路，並根據所要實現的功能用c51語言設計了軟體。由於檢測現場存在各種干擾噪聲，為了保證系統運行的穩定性和可靠性以及測量精度的要求，分別從硬體和軟體的角度出發，介紹了常用的硬體抗干擾措施以及軟體數字濾波的原理和方法。Ir drop on power grid may decrease switching speed and noise immunity of the circuits. it may even cause the circuit to fail
電源網格上的irdrop會降低器件的開關速度和噪聲容限，甚至導致邏輯錯誤。分享友人