邏輯模擬程序 的英文怎麼說

中文拼音 [luómónǐchéngxù]
邏輯模擬程序 英文
logical simulation program
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 程 : 名詞1 （規章; 法式） rule; regulation 2 （進度; 程序） order; procedure 3 （路途; 一段路） journe...
  • 邏輯 : logic
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  • 程序 : 1 （進行次序） order; procedure; course; sequence; schedule; ground rule; routing process 2 [自動...
  1. Finaiiy, the paper also has introduced the virtua1 worid of windows rs ; j { ? # - - lase / and how to map the 1ogica1 address to physica1 address in protected mode and the interrupt mechanism of protected mode, then the paper has i11ustrated that it is necessary to write virtua1 device driver ( vxd ) in order to access hardware device from the third leve1

    最後，在介紹了windows的虛擬世界，和在保護模式下如何將邏輯地址映射成物理地址，以及保護模式下的中斷機制的基礎上，闡明了在保護模式下應用程序對硬體設備操作驅動程序的必需的中間橋梁作用。
  2. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  3. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  4. In this programme, the database of many stored foods and experiential database are described by using production system, and, inexact reasoning is settled down with the method of fuzzy logic, finally, by separating the control knowledge and field knowledge, the design clue of expert in field is incarnated in the form of rules - base. the expert system created can simulate the thought and decision - making of expert in hvac field, and get the anticipative results

    該程序中用產生式規則系統建立了冷藏食品信息庫和經驗數據庫，並運用模糊邏輯方法進行不精確推理，採用控制知識和領域知識分離控制流的方法，以規則庫的形式，體現了領域專家設計思路。該專家系統模擬專家進行符號推理及選取經驗數據，得到了較好的設計結果。
  5. After discuss the structure and character of operating system qnx and inter - process communication between pc ' s running qnx or windows, the paper describes the structure, function and flow chart of mission planning software which is developed in qnx, and narrates the course of simulation co - debug experiment, dynamically showing the results of the mission planning in the case of " ocean physiognomy reconnaissance ", and proving the logical correctness and feasibility of task serial produced by mission planning

    在論述了多任務、實時操作系統qnx的結構特點以及基於qnx與windows運行的pc機之間網路進程通信的基礎上，本文描述了在qnx上開發的使命規劃軟體的結構功能和流程圖，並敘述了模擬聯調實驗的過程，動態地顯示了「海洋地貌勘測」這一案例使命規劃的結果，並證明了使命規劃所得的任務序列在實際運行中邏輯的正確性與可行性。
  6. In the modulation / demodulation circuits, cpld is selected as platform of the digital logic part, which includes series - shunt / shunt - series transform, difference coding and sample verdict

    調制/解調電路中，串並/並串變換、差分編/解碼和抽樣判決等數字邏輯部分是以cpld作為開發平臺，論文給出了實現上述功能的vhdl程序及模擬、測試結果。
  7. Then we explicate the hardware design in details, including implementing ad convert, extending multiple serial communications and external memory, and using cpld do some logic controls. thereby we implement abundance simulation interface, flexible digital interface and serial communication interface. at last we describe the software design, including software design of cpld basing on vhdl and software design of dsp

    本文首先介紹飛行模擬訓練系統的主要組成；接著說明飛控計算機整體系統方案的設計；然後詳細說明飛控計算機硬體平臺的設計，包括ad轉換、多串口通信、外部存儲器的擴展以及採用可編程邏輯器件cpld實現電路的邏輯控制等幾部分，體現了系統豐富的模擬介面、方便靈活的數字介面和串列通信介面；最後是軟體部分的編程，包括cpld部分的硬體描述語言程序設計，和dsp部分相關的程序設計。
  8. A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up

    設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。
  9. I regard qsim as a kind of constraint satisfaction problem ( csp ), and improve the qualitative simulation algorithm by constraint logic programming ( clp ). fuzzy qualitative simulation develops conventional qsim on several facets, such as representation of qualitative value, state transition rule and filtering algorithms. it bridges the gap between pure qualitative and quantitative, and improve the efficien

    前者是將定性模擬演算法看作一類約束滿足問題，用約束邏輯程序加以改進，不僅為解決定性模擬問題提供了邏輯框架，而且也是一種規范化的程序描述語言；模糊定性模擬演算法則是對純定性模擬演算法在知識描述、狀態轉移規則、過濾演算法等方面的改進，是一類半定量描述方法，有利於在定性模擬領域綜合定量信息，同時提高演算法的效率。
  10. And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned

    Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。
  11. The digital one includes spec, verilog coding, simulation, synthesis, floorplan, routeing, static timing analyze and drc / lvs check

    數字電路設計流程則包括：制定spec ， verilog代碼編寫，模擬，邏輯綜合，布局，布線，靜態時序綜合和drc lvs檢查。
  12. Laboratory simulation to stock market by using economics experiments methods is applied in this dissertation. currently, there are seldom similar records about such experiments in the civil, natural science and arts science including game theory, economics, psychology and logic have been involved in the experiment program designs and experiment outcome analysis, this is one of important innovation in this paper

    本文運用了經濟學實驗方法對股票市場進行了實驗室模擬，目前在國內鮮有類似的實驗記錄，實驗的程序設計以及結果分析將涉及博弈論、經濟學、心理學、邏輯學等自然科學以及人文科學領域，這構成了本文的重要創新之一。
  13. In the dissertation ， we discribe the implementation of large capability video data acquisition system based on pci bus of computer 。 the system is composed of data acquisiton card and corresponding software 。 the data acquisiton card include two acquisition channels ， 8 - bit digitization at rates up to 13. 5mhz 。 frist ， the architecture of the video data acqusition system is studied 。 then ， the function and implementation methode of each module are introduced in detail 。 the control module of the video data acqusition card is implemented by using of the isp technology of cpld and vhdl programming technology 。 the a / d converter used assembler to implement the initialazation programe 。 and the double buffer technology is used for large capability data acqusition. because a contiously large memory is difficult to apply in windows operating system 。 finally we use broland c + + to introduced the devleoping procedure of drivers 。

    在實際的研製過程中，利用cpld的在系統可編程（ isp ）技術和基於vhdl語言的可編程邏輯器件設計技術實現了視頻數據採集卡的控制模塊。在視頻的a / d轉換模塊，用匯編程序模擬i2c總線對初始化a / d轉換晶元。針對大容量數據採集，採用了雙緩沖技術解決wndows操作系統下難以申請到大容童連續內存的間題。
  14. The process and system utilize fuzzy logic in determining whether or not to " admit, " i. e., allocate a virtual channel ( vc ) for, new communications ( or calls ) to the node

    這個程序及系統應用模糊邏輯來決定是否要"充許" （也就是決定是否要分配一個虛擬通道） ，新的通訊連結（或呼叫）進入這節點中。
  15. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
  16. Therefore, the mathematical model for the generator sets also has two parts : one is a dynamic mathematical model used to simulate diesel engines, generators, accessories and a mathematical model for system dynamic state, that is described in the part of generator model analyzing ; the other is a logic and monitoring mathematical model used to simulate ship power station protection, alarm operation and monitoring, that is described in the part of program chart

    因此，發電機組數學模型也分為兩大類：一類是動態數學模型，用來模擬柴油機、發電機、附屬設備和系統動態狀態的數學模型，此部分在發電機模型分析中描述；另一類是邏輯和控制的數學模型，用來模擬船舶電站保護、報警、操作和控制的數學模型，此部分在程序流圖中描述。
  17. According to the function of test platform, the test platform is partition into a few modules. those modules are designed with verilog hdl and the key problems are discussed in details. the verilog codes for transmit and receive end of test platform are simulated under quartus ii 5. 0 ise, and debugged by downloading the verilog programs into ep1s25f780c and ep1s80b956c6 developing kits

    在對每一個模塊的設計要點做了詳細說明之後，採用verilog語言編寫各模塊邏輯代碼，在altera公司的quartusii5 . 0集成開發環境下，基於altera公司stratix系列fpga對各模塊及整個窄帶ldpc解碼-誤碼測試平臺進行了模擬並將發端和收端的verilog程序分別下載到altera的ep1s25f780c和ep1s80b956c6開發實驗板進行調試。
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