邏輯綜合 的英文怎麼說

中文拼音 [luózōnggě]
邏輯綜合 英文
logic synthesis
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 綜 : 綜名詞[紡織] （織布機上使 經線交錯著上下分開以便梭子通過的裝置; 綜片） heddle; heald
  • 合 : 合量詞（容量單位） ge, a unit of dry measure for grain （=1 decilitre）
  • 邏輯 : logic
  • 綜合 : 1 （歸在一起; 聯合成一個統一的整體） synthesize 2 （不同種類、不同性質的事物組合在一起） syntheti...
  1. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  2. This paper focuses on the combitional logic synthesis including two level logic synthesis and multiple level synthesis. and it is a part of control flow synthesis in a controller synthesis system. in this paper following problems are proposed and implemented : ( 1 ) implement the algorithm " espresso ", and make it suit to the system

    本文所完成的組合邏輯綜合的研究與實現是控制流綜合系統的一個組成部分，其中包括： （ 1 ）引入並實現了兩級邏輯綜合的「 espresso 」演算法，定義與系統相適應的數據結構，重新測試各種開關條件，使之適用於系統的實際應用。
  3. Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description

    邏輯綜合的功能是對組合邏輯函數的描述進行轉換和優化，生成與邏輯功能描述等價的優化的邏輯級純結構描述。
  4. In the synchronous " model, based on the idea of polygonal flux linkage locus, by means of constructing the switch state period table of three phrase voltage inverter is required. in the brushless model, the igbt ( isolated gate bipolar transistor ) switch state period table is gained by gal ( generic array logic ) which analyzes the signal of position feed - back

    在同步方式下，基於多邊形磁鏈軌跡法的思想，用作圖法求得三相電壓型逆變器的pwm波形序列；在無刷直流方式下，用gal對位置反饋信號進行邏輯綜合，得到開關管的導通規律。
  5. At last, the paper involves the flow and related data of logic simulation, logic synthesis and test vector in the risc cpu

    論文最後給出了64位vegacpu的asic邏輯模擬文件和模擬波形，邏輯綜合策略、綜合腳本和綜合結果，以及vegacpu基於atpg的測試向量設計流程和相關數據。
  6. We use different commercial eda tools in order to achieve better implementation in different design phase, which include silicon ensemble of cadence, design compiler and design primer of synopsys and so on

    在設計的不同階段使用了不同的主流eda工具進行輔助設計和驗證，包括synopsys公司的邏輯綜合工具designcompiler 、靜態時序分析工具designprimer和cadence公司的自動布局布線工具siliconensemble等。
  7. This paper first discusses the feature of vhdl, and introduces the process of very long digital system by vhdl and auto - synthesis system with the method of top - down through designing control system of color lamp, reveals that it is very important to design digital system, logic synthesis and emulation with vhdl

    本文介紹了硬體描述語言的功能特點，並通過彩燈控制系統的設計過程（給出了模擬結果） ，介紹應用硬體描述語言及自動綜合系統以自頂向下的方法進行大規模數字系統設計的過程，揭示了硬體描述語言設計數字系統、邏輯綜合和模擬等技術在數字系統設計中的重要地位和作用。
  8. In this design, codes are written in verilog - hdl, simulated in active - hdl and synthesized in synplify, based on which, this paper also give timing simulation and static timing analysis results

    採用自頂向下的設計方法，在充分了解系統的基礎上，劃分功能模塊進行行為描述、 rtl功能模擬、邏輯綜合。
  9. Finally, their applications in the logic synthesis based on the partial linear function and calculating boolean difference of logical functions are discussed

    最後討論了它們在邏輯綜合以及計算邏輯函數的布爾差分中的應用。
  10. Mostly, this design employs mentor corporation software " fpga advantage " as exploitation tool to perform design input 、 simulation and logic thesis with every level and every model to finish the fore design ； then, choices the xilinx corporation product xcv1000 of the vertex series and employ its tool “ allicance series ” to implement layout and timing simulation

    設計主要採用menter公司的功能強大的fpgaadvantage作為開發工具，進行了各個層次、各個模塊的設計輸入、模擬以及邏輯綜合，完成了電路的前端設計；然後選用xinlinx公司的fpga的vertex系列的xcv1000 ，用xinlinx公司的allianceseries工具，進行布局布線，然後再進行時序模擬，生成配置文件。
  11. ( 4 ) design and implement the alogrithm " delay balance in multiple level logic synthesis "

    （ 4 ）設計並實現了「多級邏輯綜合延遲均衡」演算法。
  12. 2. the logic synthesis process is studied in detail and the relative constraints are discussed

    2 .詳細研究了soc應用設計流程中的邏輯綜合技術方法。
  13. Product shrinkage, general sum shrinkage, elimination and extraction operators are proposed to shrink the truth vector

    但是， rm邏輯綜合和優化是困難的，尤其是對混合極性的rm邏輯，則更是這樣。
  14. So the sta ( static timing analysis ) step and the iteration between synthesis and p & r ( place & route ) were integrated in the dsm design flow

    因此，需要在深亞微米設計流程中加入靜態時序分析環節，以及邏輯綜合和布局布線之間的迭代過程。
  15. Programs with verilog language, which describe all modules of the hardware construction, have been given and succeed in the logic simulation and synthesis

    根據該演算法的硬體結構，編寫了結構中所有的veriloghdl模型，並成功進行了模擬和邏輯綜合。
  16. The digital one includes spec, verilog coding, simulation, synthesis, floorplan, routeing, static timing analyze and drc / lvs check

    數字電路設計流程則包括：制定spec ， verilog代碼編寫，模擬，邏輯綜合，布局，布線，靜態時序綜合和drc lvs檢查。
  17. In the process of design, simulation is achieved by active hdl, and synthesis is achived by symplify, and finally the chip is downloaded in quickpro

    在硬體邏輯設計過程中，藉助activehdl進行硬體邏輯前後模擬，使用symplify工具進行邏輯綜合，最終在quickworks下生成fpga晶元。
  18. At the logic synthesis stage, we make some research on the principles of logic synthesis at first, then by utilizing tsmc0. 25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2. 25v, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15. 3ns and the chip area is 0. 395mm2

    在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然後利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，採用與模擬時相同的時鐘，關鍵路徑為15 . 3ns ，晶元面積為0 . 395mm ~ 2 。
  19. In which, we use cubic symbol for describing the logic function of a network in well - balanced state, then use sharp - product operation for constructing disjoint minimal path set of network. and a dps algorithm for finding out the minimal path set is also presented

    研究了網路可靠性分析的不交和演算法，應用計算機輔助邏輯綜合技術實現最小路徑的不交化；並給出一個搜索網路所有最小路經的dfs演算法。
  20. High - level synthesis has been developed on the base of logic synthesis. it starts from the behavioral design description of high - level and outputs the structural description with lower level as a result. so the design complexity can be simplified and design efficiency can be raised

    高級綜合是在邏輯綜合的基礎上發展而來的，它從高層次的行為描述開始，自動綜合出低層次的結構描述，從而降低了設計復雜度，提高了設計效率。
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