邏輯觸發 的英文怎麼說

中文拼音 [luóchùfā]
邏輯觸發 英文
logictoggle
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 觸 : Ⅰ動詞1 （接觸） touch; contact 2 （碰; 撞） strike; hit 3 （觸動） touch 4 （感動） move sb ; sti...
  • 發 : 名詞（頭發） hair
  • 邏輯 : logic
  • 觸發 : detonate by contact; touch off; trigger; strike
  1. Design of a flip - flop circuit within digital logic analyzer based on fpga

    的邏輯分析儀觸發電路的設計
  2. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析，提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  3. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。
  4. According to the requirements of static compensator ( statcom ) to triggering pulse generator, an autonomous triggering system for statcom was developed based on complex programmable logic device ( cpld )

    針對靜止無功補償器（ statcom ）對觸發脈沖發生電路的要求，利用復雜可編程邏輯器件（ cpld ）開發了一種自治型statcom觸發系統。
  5. By analyzing the equivalent circuit of statcom, the basic requirements to the triggering system was pointed out, and the cpld - based functional structure for triggering pulse generator was established

    通過對statcom工作原理與等效電路的分析，指出了statcom對其觸發系統的基本要求，建立了基於cpld的觸發脈沖發生電路的功能邏輯結構。
  6. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  7. In this paper necessity for upgrading of main trigger of beijing spectrometer is described. the table look - up method is used for programmable trigger table decision

    摘要介紹了北京譜儀主觸發系統的改進及用查表法實現主觸發系統的觸發表判選邏輯。
  8. A meta - trigger table is created to fulfill user - customization because in reality business conversion functions are changeable and unforeseeable

    針對業務轉換函數的不可預見性，通過建立元觸發器表，實現了業務邏輯轉換函數的可定製。
  9. Under the requirement of the relevent study, the research group decided to design a programmable multifunctional module in vme standard

    根據方案設計階段的需要，觸發課題組提出了設計一塊基於vme總線的多功能可編程邏輯插件的設想。
  10. The second example is a implementation of versatile digital waveform generator reveiver, which can be used as a means to test track segment finding logic and global decision logic, and other logics

    該信號發生器可以產生任意波型的數字脈沖信號，可以用於主觸發和主漂移室尋跡邏輯的調試與測試，為其它插件的調試創造條件。
  11. About the transducer between rotor and power source, the paper uses a cycloconverters, comprising 36 thyristors, and analyzes the control of circumfluence, the method of cosine crossing, the producing of trigger pulse, zero current detecting, commutating logic control and its mathematical model

    對雙饋電機轉子側所接變頻器類型，本文也進行了對比分析，對選用的循環變流器的原理還作了進一步的分析，包括環流控制方法、餘弦交截法原理、觸發脈沖產生、零電流檢測和換向邏輯控制等部分，並給出了其數學模型。
  12. This course consists of lectures and labs on digital logic, flipflops, pals, counters, timing, synchronization, finite - state machines, and microprogrammed systems

    本課包括了數字邏輯、觸發器、 pal （可編程邏輯陣列） 、計數器、時序、同步、有限狀態機、和微控制系統方面的講課與實驗。
  13. In meantime, the all sub - circuits are also designed and emulated carefully including error amplifier, voltage reference circuit, voltage comparator, rs type flip - flop, soft - start circuit, sawtooth - wave generator, pwm comparator, current added circuit and so on

    其次對控制器內部晶元的各個模塊誤差放大電器、自舉電流電路、電壓基準源、電流求和電路、 rs觸發器和驅動電路等模塊進行了具體的設計和模擬的邏輯功能做了解釋。
  14. The paper analyses its key circuit and software program structure. this full - digital controller is made up of dsp and implements single neuron adaptive pid computation, current pi computation, logical determination, pulse - fire and procession of protective signal etc. it also improves the reliability and availability of this control system

    本課題對控制器主要的電路結構及程序結構進行了分析，以dsp為核心組成的全數字式控制器完成了電流pi演算法計算，單神經元自適應pid演算法計算、邏輯判斷、脈沖觸發以及系統保護信號的處理等，提高了控制器的可靠性和可操作性。
  15. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  16. This section addresses the timing relationships between transitions of one or more input signals that are necessary to ensure device functionality and applies only to sequential - logic devices ( e. g., flip - flops, latches, and registers )

    本節為一個或更多輸入信號之間的時序關系提供尋址，這些輸入信號是使器件發揮作用的必須信號，並且只應用於順序邏輯器件（比如觸發器、鎖存寄存器和寄存器） 。
  17. The fire method is triggered for the rule execution and the necessary logic is provided for the execution of business rules, such as selection of the manufacturing plant

    觸發fire方法用於執行規則，並為執行商業規則如加工工廠的選擇提供了必要的邏輯。
  18. According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design

    為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。
  19. Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired

    在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。
  20. Already i can see the chain reaction the chemical precursors that signal the onset of an emotion designed specifically to overwhelm logic and reason

    我看得到你在想什麼，你大腦里的化學物質觸發情感，讓情感戰勝理性和邏輯。
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