邏輯門 的英文怎麼說

中文拼音 [luómén]
邏輯門 英文
logic gate
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 門 : Ⅰ名詞1 （房屋、車船等的出入口 ） entrance; exit; door; gate 2 （形狀或作用像門的東西） switch; va...
  • 邏輯 : logic
  1. （ lesson 1 how does a logic gate in a microchip work

    第一課晶元上的邏輯門是如何工作的？
  2. Realization of spice model logical gate in electronics workbench

    模型邏輯門的實現
  3. Secondly, the encoder circuit of quasi - cyclic which can realize low encoding complexity are designed and implemented. three encoder circuit are designed respectively with feed shift - registers and logic gates : sraa - based serial qc - ldpc encoder ; sraa - based parallel qc - ldpc encoder ; two - stage qc - ldpc encoder

    採用反饋移位寄存器與邏輯門設計了三個典型的編碼器電路:基於sraa電路的串列準循環ldpc碼編碼器;基於sraa電路的并行準循環ldpc碼編碼器;二階編碼電路。
  4. A novel quantum neural computational model is constructed based on the universal quantum gates unit ( i. e. phase - shift gate and controlled not gate ), which acts as the basic computational component

    研究以通用量子邏輯門組（即相移門和受控非門）作為計算基函數，構造新的量子神經計算網路模型。
  5. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  6. The teaching difficulty of the course of digital circuit basis mainly focuses on some knowledge of components, for example, semiconductor basis, separation and integration logic gate circuits

    摘要《數字電路基礎》課程的教學難點主要集中在半導體基礎、分立和集成邏輯門電路等元器件知識部分。
  7. In the third part, gives a new fft algorithm for realization ofdm modulation in fpga

    第三部分為在的現場可編程邏輯門陣列（ fpga ）上實現ofdm調制模塊。
  8. The synthesis of arbitrary boolean functions based on threshold logic gate

    基於閾值邏輯門的任意布爾函數綜合
  9. Saturating logic gate

    飽和邏輯門
  10. Universal logic gate

    通用邏輯門
  11. The output signal can then be amplified ( possibly with a logic gate at this point ) to drive the converters

    電路輸出的信號需要放大后再使用（例如用邏輯門） 。
  12. On one hand, realizing and controlling a quantum logic gate is attended by people because of its inportance for quantum computation

    一方面，量子邏輯門的實現和控制因其在量子計算中的重要性而備受人們所重視。
  13. The popular oscillator design which uses a resistor, one or more logic gates, a quartz crystal, and a couple of capacitors should never be used

    一般振蕩器設計都用一個電阻、一個或幾個邏輯門、一個晶體、兩個電容，在這里絕對不能用。
  14. Using the evolution method, by solving the master equation analytically, we find that as the accuracy to implemente the logic gate operation is improved, the time needed is prolonged

    可是在量子邏輯門操作精度提高的前提之下，進行一次邏輯運算的時間被延長。
  15. An embedded merging scheme for h. 264 avc motion estimation. in international conference on image processing, barcelona, spain, september 14 - 17, 2003, 1 : 909 - 912

    本文中的硬體電路主頻可以達到150兆赫茲，電路面積大約為212k邏輯門，能較好的完成可變塊大小的運動估計。
  16. Sorting algorithm can solve logic gate circuit for more fanout, more loop nestification and feedback alternately. we sort these nodes according to their joint relationship by the sort algorithm that can determine the priority order of digital circuit simulation and give the feedback chain

    排序演算法可以解決具有多扇出、多迴路嵌套及交叉反饋的邏輯門電路，按照其連接關系進行排序，並給出其中的最大反饋鏈。
  17. In order to enhance the applying efficiency of cl, the cause of premature convergence in binary - coded genetic algorithms ( gas ) is analyzed in this dissertation. the drawback of conventional mutation operator in preventing premature convergence is subsequently pointed out. whereafter, a genetic algorithm, which can be implemented via general logic gate circuit, is proposed

    為了提高計算智能的應用效率，本文分析了二進制遺傳演算法中早熟收斂的成因，指出了傳統的變異運算元在防止早熟收斂方面的不足，提出了一種能有效預防早熟現象的二元變異運算元，並在此基礎上提出了一種便於用常規邏輯門電路實現的遺傳演算法。
  18. With the rapid development of semiconductor, digital integrated circuit ( p, memory, standard logic gates, etc. ) and advance computer technology, the various measuring instruments ( virtual instruments ) with the powerful function of pc are produced in different industrial and scientific research fields. as we all known, the traditional instruments are usually built with discrete components and small scale ics, the disadvantages are obvious in system design, debugging and maintenance

    隨著半導體技術與數字集成電路（微處理器、存貯器以及標準邏輯門電路等）技術的迅速發展，特別是隨著計算機技術的發展，在工業生產和科學技術研究的各行各業中，人們利用pc機的強大處理功能代替傳統儀器的某些部件，開發出各種測量儀器（虛擬儀器） ，傳統儀器的數字邏輯部分多是採用分立集成電路（ ic ）組成，分立ic愈多，給系統的電路設計、調試及維護帶來諸多不便。
  19. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory. in 1995, barenco showed that almost any two - bit gate is universal, so building a feasible two - bit logic gate is the first step to engineer a quantum computer. in principle, the quantum bit can be carried by any two states system

    在眾多的量子計算機模型中目前討論最廣泛的是量子計算機門組網路模型，量子計算機門組網路模型是經典計算機門組網路結構的量子推廣，它是根基於barenco等人所證明的「一個兩比特受控操作和對單比特進行任意操作的門可以構成一個『通用量子邏輯門組』 」之上的。
  20. Due to the importance of the interferometer in implementing the logic gate operations, the coherent time of the system used as quantum bit must be as long as that to carry out the logic gate operations at least. the trapped ions meet the above demands, so it is the best candidate

    由於離子阱中超冷離子是處在一個近乎與世隔絕的空間中，它與外界的相互作用極弱，所以由環境引起的消相干近似可以忽略，因此囚禁離子阱中超冷二能級離子成為實施量子邏輯門操作的首選。
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