鎖存電路 的英文怎麼說

中文拼音 [suǒcúndiàn]
鎖存電路 英文
circuit, latch
  • : Ⅰ名詞1 (安在開合處使人不能隨便打開的器具) lock 2 (姓氏) a surname Ⅱ動詞1 (上鎖) lock up 2 ...
  • : 動詞1 (存在; 生存) exist; live; survive 2 (儲存; 保存) store; keep 3 (蓄積; 聚集) accumulat...
  • : Ⅰ名詞1 (有電荷存在和電荷變化的現象) electricity 2 (電報) telegram; cable Ⅱ動詞1 (觸電) give...
  • : 1 (道路) road; way; path 2 (路程) journey; distance 3 (途徑; 門路) way; means 4 (條理) se...
  • 電路 : [訊] circuit (ckt); electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The channel counter and decoder provide the channel select information to the data latch and transmit logic circuits.

    通道計數器和解碼器向數據和傳送邏輯提供通道選擇信息。
  2. Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ). in this paper, some means to harden the devices against these phenomena are used. guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup

    在本文設計中,採用雙環保護結構,大大的降低了cmos集成對單粒子閂效應的敏感性;對nmos管採用環型柵結構代替傳統的雙邊器件結構,消除了輻射感生邊緣寄生晶體管漏效應;採用附加晶體管的冗餘結構,減輕了單粒子翻轉效應的影響。
  3. The dac consists of analog circuit blocks and digital circuit blocks, so it is a mixed signal circuit. because the digital part is simple comparatively, we use the same method as analog part to design it

    採用模塊化的設計方式實現數據快速轉換,主要包括流源矩陣模塊、模塊、譯碼模塊、帶隙基準壓源模塊及流開關網模塊。
  4. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後,在具體的子adc設計中,對比各比較器類型的優缺點,並基於預放大快速比較理論,提出一種新型高速低功耗預放大比較器拓撲;根據adc系統所允許的參考壓最大波動限制,在回饋噪聲對輸入參考平的影響和功耗之間折衷,確定優化的參考阻串阻值;根據不同級精度的編碼要求,設計出時鐘控制編碼
  5. After that, the hardware circuit, especially some of the key parts, is investigated in detail. the following processes are also investigated in detail : empoldering the four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data with vhdl ( very high speed integrated circuit hardware description language ) ; empoldering the serial interface and the data collection software in pc with borland c + + builder

    接下來詳細介紹了使用vhdl語言開發fpga晶元的細分、辨向、計數、以及串列傳輸處理等全部功能;用borlandc + + builder開發了pc機上的串列介面、數據採集軟體;設計並製作了fpga晶元及其外圍板。
  6. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究,結合系統性能確定了子adc的指標要求,詳細討論並設計了子adc單元模塊的設計,包括預放大比較器,參考阻串和時鐘控制編碼
  7. Abstract : the hidden perils and troubles of safety existing in the interlocking circuit between the tipper in the raw material area and the railway signal system in wisco have been analyzed one by one and causes to their occurrence found out and the technological theory and counter measures to solve those problems comprehensively expounded and better working performance and reliability on the improved interlocking circuit achieved

    文摘:針對武鋼原料區原翻車機與鐵信號聯在的安全隱患和缺陷,一個一個地進行剖析,找出它們產生的根源,全面系統地論述了解決這些問題的專業技術理論及其具體的改進措施,使改進后的翻車機與鐵信號聯性能良好、工作可靠。
  8. Individuals who believe that their intellectual property rights have been infringed either on the internet or through online services provided by ctm may contact ctm, directly or through their authorized agents, and request that the infringing material be removed or access to it blocked

    如果任何人士認為其知識產權在澳門訊的網際網服務或聯線作業服務中受到侵犯,可直接或透過授權代理人與澳門訊聯絡,要求移除或封取侵犯知識產權的資料。
  9. Firstly, computer model of mdrlg is set up for simulation purpose. by simulation about the two output signals of mdrlg, four basic waveforms between the two signals in lock - in area are found out and the fact is discovered that the old phase - demodulation circuit introduces errors when it is used for demodulating two of the four basic waveforms

    本文首先建立了機抖陀螺的計算機模擬模型,利用該模型對陀螺兩計數信號及原有鑒相進行了模擬,發現兩計數信號過區時在四種基本波形,且原有鑒相對其中兩種波形產生鑒相誤差。
  10. Controlling system is composed of drive circuit, locking memory, shift register. temperature compensating circuit and drive power circuit are also needed

    控制系統是由驅動器、移位寄器等組成,此外還需要溫度補償和驅動,本文對控制系統進行了詳細的論述。
  11. The time division circuit and latch counter are integrated in one chip of programmable logic device, which makes the size greatly decreased

    同時採用cpld晶元實現了時間分割和計數鎖存電路,有效地減小了體積。
  12. High ? speed synchronized latch circuit and special clock driver are used, which adapt to the requirement of quick data - transformation with high accuracy and low power

    採用高速同步鎖存電路和特殊結構的時鐘驅動,在保證精度和功耗設計要求上,實現數據快速轉換。
  13. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器,結合外部的模數轉換和數模轉換、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面,設計了集採集、轉換、控制於一身的isa卡。
  14. The host pc and terminal machine communicate with each other by udp, and the reading of ic card is through serial port. the measuring apparatus consists of analog switch, ad converter ads1256 circuits while the filtering apparatus is composed of latch 74hc374

    控制箱通過udp協議和pc通訊,通過串口讀寫ic卡;檢測儀主板主要由模擬開關和ads1256的組成;分選儀主板則主要是由74hc374器組成的分選
  15. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是設計要考慮的主要因素,不同的形式具有不同的優缺點,如cmos互補邏輯功耗低,面積小,速度相對較慢; scfl (源極耦合fet邏輯)速度高,功耗和面積較大。所以要針對具體設計需要選用適當的形式或其組合結構,以滿足設計要求。觸發器是分接器的基本組成單元,建立時間和保持時間是影響速度的關鍵,所以減小建立時間和保持時間是觸發器設計的主要目標,本文著重介紹了scfl器的設計和優化方法。
  16. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象,在詳細分析原設備的系統結構和功能實現方式的基礎上,指出該機型在使用過程中在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題,同時結合系統的低功耗需求和優化人機介面設計,本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案:在cpld中實現信號音分頻和計時頻率生成、 20用戶led狀態控制; cpld與單片機以總線介面方式實現譯碼、數據和控制信號功能的vhdl設計;基於低功耗設計的器件選型方案和單片機待機模式設計;人機介面的lcd菜單操作方式。
  17. Recently, the n / n + and p / p + epitaxial structures have been applied in the study and production of microwave transistor and ultra - large - scale integrated circuits ( ulsi ), and the memorial maintain time of dynamic random access memory can be improved, latch - up effect and soft - error induced by a particles can be resolved through the combination of epitaxy and ig

    採用這種結構與ig工藝相結合,能夠大大地提高動態儲器dram的記憶保持時間,是解決中閂效應( latch - up )和粒子引起的軟失效( soft - error )的最佳途徑。
  18. In this paper design of some circuit including in a / d circuit is also analyzed, such as front analog circuit, sample clock circuit and data flip - latch circuit

    同時對高速轉換器件及轉換中包括前端模擬、采樣時鐘、後端數據等輔助設計進行了分析。
  19. Wide - ranging improvement measures were recommended, covering the storage and safe custody of fare box keys, coin counting and accounting procedures, the design of the record cards, the custody of staff uniform, floor plans of the coin counting room and cashier office, not the least the installation of closed circuit televisions and monitors

    審查報告提出了一連串的改善建議,從錢箱匙及箱膽的放和保安數錢及入帳程序收入紀錄卡的設計職員制服的監管點數室及出納部的平面圖至閉視的裝置和監察等。
  20. If chaos or network theories are right, a chance of large cascading failures is inherent to stressed or highly interconnected systems

    如果混沌或網理論是正確的,在負載壓力大或高度聯結的系統里,大規模連的機率總是在的。
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