鎖相時鐘 的英文怎麼說

中文拼音 [suǒxiāngshízhōng]
鎖相時鐘 英文
phase-locked clock
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 相 : 相Ⅰ名詞1 （相貌; 外貌） looks; appearance 2 （坐、立等的姿態） bearing; posture 3 [物理學] （相位...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. We have developed a high precision wavemeter with an accuracy of 2 10 ^ ( - 8 ) in measuring vacuum wavelength, and a frequency measurement instrument by femtosecond modelocked laser with an accuracy of commercial cs standard

    為了適應研究工作的需要，研製了高精度激光波長計，測量真空波長的準確度可達2 10 ^ （ - 8 ）的量級，同時研製了飛秒鎖模激光的測頻裝置，目前的測量精度可與小銫鐘的精度相同。
  2. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  3. In this paper, a clock recovery system that based on phase control technology is studied

    本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。
  4. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  5. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  6. The programmable logic device ( pld ) is applied in this system for controller as well as data storage

    本系統採用鎖相型頻率合成器作為超高速模數轉換器的時鐘源。
  7. The paper compares some algorithms on rs decoding, makes improvements based on the me algorithm, removes the modifying step in decoding truncate rs code, corrects unsuitable statements in the related papers, and parameterizes the rs decoding module, reducing its area by 20 %. the paper overcomes the signal integration problem in multi - clock design, greatly lowers the phase jitter without area increase, introduces pll to adjust rate for the first time, and parameterizes the module

    本文比較了實現rs解碼的幾種演算法，並在me演算法基礎上進行改進，創造性的去掉了縮短碼解碼中的校正環節，糾正了有關論文中的不當論述，並將rs解碼模塊進行了參數化設計，同時也將rs解碼的規模縮小了20 ；克服了多時鐘設計中的信號完整性難題，在沒有增加模塊面積的條件下，大幅降低數據的相位摘要抖動，首次引入鎖相環來調整速率。
  8. This paper based on control theory, according to the conception of phrase lock loop and direct digital synthesis, we designed the clock circuit. it realizes the amalgamation of kinds of the ways about clock, which make it has some superiority

    本論文在控制理論的基礎上，以鎖相頻率合成和直接數字頻率合成作為設計思想，搭建時鐘控制電路，在業界實現了多種時鐘控制電路實現方法的融合與統一，具有一定的優越性和領先性。
  9. Digital phase lock loop is used in this section to synchronize to an incoming serial data stream

    數據接收解碼模塊中使用了數字鎖相環技術從輸入數據碼流中提取出同步時鐘信號。
  10. Based on all these above, two schemes which use digital methods to measure the jitter of a pll clock of 2. 048mhz are presented and accomplished

    在此基礎上，提出並實現了測試一固定頻率（ 2 . 048mhz ）鎖相時鐘抖動的方案。
  11. A high precise gps glonass synchronization clock pll

    同步時鐘鎖相環
  12. An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,

    提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  13. But to design and integrate a clock generator into a chip is a far cry from the out - chip one

    文中研究的鎖相環時鐘發生器就針對該要求而設計。
  14. The pll clock generator, which has been integrated in " line ", will be taped out through tsmc 0. 25um mpw ( multi - project wafer ) project

    該鎖相環時鐘發生器採用了tsmc0 . 25umcmos製造工藝，它將和「 line 」晶元一起在tsmc的多晶圓（ mpw ）項目下流片。
  15. A monolithic clock synthesis pll, which is expected to be a reference 800mhz clock generator in accelerometer system, has been designed and characterized in this paper

    本文設計了一種採用鎖相環頻率合成技術實現的800mhz時鐘發生器，用作加速度傳感器讀出電路的基準時鐘信號。
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