鎖相邏輯 的英文怎麼說

中文拼音 [suǒxiāngluó]
鎖相邏輯 英文
phase locked logic
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 相 : 相Ⅰ名詞1 （相貌; 外貌） looks; appearance 2 （坐、立等的姿態） bearing; posture 3 [物理學] （相位...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 邏輯 : logic
  1. We design inversion control circuit with cmos figure pll cd4046 act as core and microprocessor 80c196kc act as assistant controller. adopting a control method that combine fuzzy controller and pll control, improve induction heating power succeed in startup. adopting electric current voltage pair closed loop feedback design, with trough route capacitance voltage and trough route electric current act as pair closed loop feedback signal, guarantee induction heating power output accuracy

    並對系統主電路的元器件參數進行了詳細的計算；設計了以cmos數字鎖相環cd4046為核心、以80c196kc作為輔助控制器的逆變控制電路；採用了模糊邏輯與鎖相環相結合的控制技術，提高了電源的啟動成功率；採用電流、電壓雙閉環反饋方案，採用槽路電容電壓和槽路電流作為反饋信號，從而保證了電源功率的輸出精度。
  2. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  3. This thesis introduce the design of dsp control for three phase inverter, witch includes digital realization of pwm control, digital pll, swap control between inverter and utility, and communication with mcu. base on inverter model, inverter output l - c filter is investigated, and double - loop control scheme with tms320lf240 are selected

    本文主要介紹了基於dsp控制三相逆變器系統的總體設計方案，其中包括spwm控制的數字實現、逆變器輸出電壓的數字鎖相、逆變器與旁路間的切換邏輯及逆變器與上位機的通訊。
  4. An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,

    提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  5. Utilizing phase locked loop technique with complex programmable logic devices ( cpld ), a method to perform high - speed data acquisition, storage and transmission for transformer testing, which solves the problem of data acquisition for high frequency band, is proposed

    摘要提出了利用鎖相環技術結合復雜可編程邏輯器件（ cpld ）實現對變壓器測試信號的高速採集、存儲、傳輸的方法，很好地解決了對變壓器高頻特性信號的採集。
  6. This paper analyzed the logic in detail and realized the logic automatically with the method of heuristic search based on width - first searching

    本文詳細分析了防誤操作閉鎖邏輯的特點，並用啟發式搜索和寬度優先搜索相結合的搜索方法實現了該邏輯的自動生成。
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