鐘的同步 的英文怎麼說

中文拼音 [zhōngdetóngbù]
鐘的同步 英文
synchronization of clocks
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 的 : 4次方是 The fourth power of 2 is direction
  • 步 : Ⅰ名詞1 （步度; 腳步） pace; step 2 （階段） stage; step 3 （地步; 境地） condition; situation; st...
  1. Some message described in the thesis, such as the basic structure of gps - oem, the consists of positioning system, the binary format of almanac and ephemeris, the method and the skill of processing orignal data through singlechip, and so on, is very useful for studying gps and its applications in integrated navigation, and re - development on gps - oem

    同時亦可與gis （地理信息系統）配套使用，實現在crt上地圖背景下的運動軌跡顯示。第二個產品， gps時鐘/同步系統，利用全球衛星定位gps衛星的標準utc時間，可在全球得到同步的準確時間。設備採用motorola的12通道gpsoem接收機。
  2. The tft lcm driver signals were enable signal and fiducial clock signal, which were strict with synchronization

    驅動信號主要為使能信號和基準時鐘信號，並要求二者具有嚴格的同步性。
  3. As concerning to the interference condition between different transmit / receive channels in the system, a detailed error analysis is given, and the clock and synchronization scheme is explicated. the measure adopted to enhance phase clock ' s precision is explained

    本文對超聲相控陣系統中各通道發射/接收的相干條件進行了詳細的誤差分析，闡明了本系統採用的時鐘和同步方案，以及改進相控陣時鐘精度的方法。
  4. Bits supplies the synchronous timing signal to these equipments inside the telecommunicationt building, such as dps, atm, no. 7, dxc, tm & adm in sdh, don and in etc. the related techniques are involved in the content of synchronization ne twork, timing distribution, the timing signal transportations x impairments etc. the second chapter tells the structure and the function of the building integrated timing system. the third chapter summarizes the digital synchronization network techniques, which emphasizes the basic concept of synchronization networks analyzes the necessity of building the synchronization network and introduces all kinds of synchronization methods. the fourth chapter represents the transportation of the synchronization signal

    本文第二章講述了通信樓綜合定時系統的構成及作用：第三章概述了數字同步網技術，著重描述了同步網的基本概念，分析了建立同步網的必要性，講述了各種同步方法；第四章闡述了同步定時信號的傳輸；第五章介紹了bits設備所支持的同步狀態消息；第六章、第七章為本文的重點，通過對時鐘信號建立數學模型，從理論上分析時鐘內部噪聲和相位瞬變產生時鐘定時信號損傷的原理，企圖尋找到更好地控制頻率漂移的方法。
  5. That is to say, the test system can be connected easily with other systems and be installded with the setup softwares by using socket communication. what is more, the scheme that the thesis mentioned just uses adapted ieee1588 to synchronize the collection machines ? network nodes, because there is no need to implement the whole ieee1588 in the simple enviroment, and an extend manner to implement the whole protocol is discussed in the master / slave communication

    本文對飛機測試系統外總線進行綜合分析后，並在理解了ieee1588的時鐘同步原理的基礎上，對ieee1588進行了裁減，並將裁減后的ieee1588協議應用到各數據採集器的同步策略中，使各採集器之間能達到精確的時間同步，進一步提出了在主/從方式的測試系統中實現完整ieee1588的擴充同步方案。
  6. Therefore, it is necessary to mount timing system alone in synchronization network node and the place where there are more telecommunication equipments and the important hinge, which supplies the primary synchronization signal conformed to the standard

    因此，有必要在同步節點處或通信設備較多的地方以及通信網的重要樞紐處，單獨設置時鐘系統，對所在的通信樓的設備提供合乎標準的同步基準信號。
  7. The equilibrium thermal radiation in a flat space - time or a curved space - time behaves like planck black spectrum represented with coordinate quantities. we regard the fact that the radiation from a thermal equilibrium system shows planck black spectrum as a basic physics law, from which it is demonstrated that the transitivity of clock rate synchronization is equivalent to the zeroth law of thermodynamics. the condition of clock rate synchronization is weaker than that constructing simultaneity surfaces. in the space - time satisfying the condition of clock rate synchronization, the zeroth law of thermodynamics is valid. on the other hand, in the space - time where the zeroth law is valid, one can define an identical clock rate

    平直或彎曲時空中的平衡熱輻射，表現出用坐標量表示的普朗克黑體譜.把熱平衡系統的輻射具有普朗克黑體譜作為一條基本的物理規律，以此為基礎，論證鐘速同步的傳遞性等價于熱力學第零定律.鐘速同步的條件比建立同時面的條件要弱.滿足這一條件的時空，熱力學第零定律在其中成立.第零定律成立的時空，一定可以定義統一的鐘速
  8. Requirements for clock and synchronization equipment used in the digital network

    數字網內時鐘和同步設備的進網要求
  9. Then some key techniques in mpeg - 2 and mpeg - 4 recommendations are studied and compared in detail, including motion estimation, motion compensation, discrete cosine transform, inverse discrete cosine transform, variable length coding and layered description of picture and code stream

    然後深入研究了mpeg - 2建議的視頻編碼標準，包括ts流、 ps流、時鐘恢復、視頻與音頻的同步、基於場的運動補償、 dct及變長編碼。
  10. However, we noticed that many consumer pcs had internal clocks with a different speed, leading to desynchronization

    但是，我們注意到一些機器的內部時鐘速度不一樣，這樣會導致錯誤的同步。
  11. For examp1e, the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion

    其中，編排級數法確定了組合邏輯的層次關系；通路敏化輸入波形方法決定了最小時鐘周期；基於周期的同步時序電路的模擬演算法加快了模擬的速度等。
  12. Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment

    Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。
  13. Compatibility test procedures of clock and synchroni - zation equipment of digital switch introduced into di - gital network

    數字交換機的時鐘和同步設備進入數字網的兼容性測試方法
  14. Then, two fault - tolerant - orient real - time operating system ( rtos ), which are tested as flight critical software applications and reliable, are presented. in addition, the synchronization between the two computers in fadec system, which includes synchronization of real time clock ( rtc ) and synchronization of task layer, is designed

    基於這種全新系統結構，完成了fadec系統軟體非相似技術容錯結構系統設計；完成了高可靠性非相似嵌入式實時操作系統（ rtos ）的選型；完成了fadec系統雙機同步（包括時鐘級同步和任務級同步）設計。
  15. In addition, nodes in the system need be synchronized periodically to properly work, where dgps also plays an important role. the 1pps ( one pulse per second ) signal output from dgps provides an easy way to accurately time using an ordinary clock

    此外，系統的各節點需要同步工作，而dgps接收機此時同樣起到了重要的作用，其輸出的秒脈沖（ 1pps ）信號使系統只利用一個普通的時鐘就實現了高精度的同步。
  16. Since it uses only packet inter - arrival times for estimation, itp does not require synchronous clocks between the sender and receiver

    並且， itp演算法通過測量數據包到達接收方時間的差值得到網路的可用帶寬，因此，不需要發送方和接收方之間時鐘的同步。
  17. The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition

    表2中第三行表示計數器的同步平行的加載，和表明如果s1和s0為高電平，那麼它就不是連續輸入，在時鐘由低向高跳變后，在a端的數據輸入則在qa端輸出，在b端的數據輸入將在qb端輸出，等等。
  18. And software method can resolve d channel ' s work for its less data communication ; 3 ) cpu 80c152 is synchronized with mc145572 by a simple synchronous circuit, avoiding the complex fpga interface circuit ; 4 ) data transmission use dma, which reduces the delay of data transmission and cpu occupying ; 5 ) 8bit software look - up table method can achieve 16bit crc quickly, which reduces the resource of both hardware and software

    對通信數據量相對小的d通道，採用軟體實現裝幀與解幀。第三，採用結構簡單的外部同步時鐘電路實現80c152和接入晶元mc145572的同步傳輸，巧妙地避開了復雜的fpga介面電路。第四，利用dma技術完成數據快速收發，降低了數據傳輸時延及cpu佔用率。
  19. System clock provides several synchronism clocks for every sub - circuit. reset circuit assumes that digital circuits have an initial state and self start

    系統時鐘電路分出多個同步頻率，以提供不同數字子電路的同步時鐘。
  20. Analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm. the system use input clock as system clock and use parallel structure in system to provide flexible speed

    採用適合fpga特點的溢出控制設計方法;改進傳統的寄存器交換法re （ registerexchange ）的倖存路徑管理設計方法;全系統採用輸入數據的同步時鐘作為系統時鐘，系統內部採用全并行的方式，以提供靈活的速度。
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