除法器 的英文怎麼說

中文拼音 [chúfǎqì]
除法器 英文
divider
  • 除 : Ⅰ動詞1 （去掉） get rid of; eliminate; remove 2 [數學] （用一個數把另一個數分成若干等份） divide:...
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 法器 : [宗教] musical instruments used in a buddhist or taoist mass
  1. Then we show an algorithm design of the elliptic curve crypto based on galois field. as a main part, the design theory and concrete solution of it are presented step by step, ic chip design method for implementation of the algorithm is described in detail

    設計完成了一種基於有限域的橢圓曲線加密演算法，主要包括適合於168bit橢圓曲線加密的有限域乘法、加法、除法器的實現； 4
  2. Method of measuring gas leakage of electrostatic precipitators

    電除塵器漏風率測試方法
  3. F37 type return current damp dust catcher

    F37型返水濕法除塵器
  4. F37 water - cycle wet method dust catcher

    F37型返水濕法除塵器
  5. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  6. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  7. The number of error symbols that can be corrected by the decoder is 2. the design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation

    Rs （ 256 ， 252 ）譯碼器的設計過程主要包括輸入數據的存儲、伴隨式的計算、乘法器和除法器的設計、關鍵方程的求解等幾個步驟。
  8. Water shutoff agent dsz - a is composed of inorganic particle. its specialities are low cost, easily flow, high strength and long valid period. the agent suits non - selective water shutoff in sand formation. dsz - a not only can plug high water - bearing formation, but also can plug case leakage. dsz - a has been applied on site and gotten good effect. it is a agent which has wide prospect

    井下護泵除砂裝置主要用於產液氣量高，出砂能力大，利用常規裝置、常規方法很難治理的井.它的設計是建立在丟手封隔器卡封的基礎上，將液體攜砂能力由地層進入泵管轉變為先過濾（雙層激光割縫篩管部分） ，再在除砂器內靜態沉澱、由單流閥排入井底等一系列除砂護泵優點.本文著重介紹了井下護泵除砂裝置的工作原理與應用情況
  9. Secondly the detection precision is only related to the synchronization phase but not to the amplitude of the mainline voltage because that it uses the optimized pulses synchronous with the mainline voltage as modulation signals. thirdly it decreases the requirement of the input low pass filter and eliminates the error resulting from the direct component and even harmonics of load current. the most significant merit is that it can eliminate the effect of a few low order odd harmonics and the detecting circuit is easy to be implemented

    模擬和實驗結果表明該方法的主要優點有：不需使用乘法器進行信號調制，調制信號採用與電網電壓同步的優化特定脈沖，其檢測精度只與同步相位有關，而與電網電壓幅值無關；降低了對輸入低通濾波器的通頻帶要求，直流和偶次諧波分量對檢測精度沒有影響；突出的優點是可以消除有限個低奇次諧波對檢測結果的影響。
  10. Measuring method for performances of wet dust collectors

    濕式除塵器性能測定方法
  11. Measuring method for performance of wet dust collectors

    濕式除塵器性能測定方法
  12. Classification and specification for bag filters

    袋式除塵器分類及規格性能表示方法
  13. Back - blow wet method dust catcher

    反水濕法除塵器
  14. Suppose that you receive the calculator for testing and find that besides addition, subtraction, multiplication, and division, it also performs square roots

    假如您收到的測試用計算器除了能加法，減法，乘法，除法以外還能做平方根運算。
  15. A straight inlet baghouse which can effectively reduce energy consumption of equipment in operation and lengthen the service life of fabric bags, as well as gas flow structure in the tank body have been presented, and numerically simulating the gas flow distribution in the tank body being carried out by using calculated flow dynamics ( cfd ) method, providing a method and parameters for adjusting the gas distributing plates structure to realize reasonable flow rate distribution in the tank body

    摘要介紹了能有效降低設備運行能耗、提高濾袋壽命的直通式袋式除塵器及其箱體氣體流通結構，並利用cfd方法對箱體流量分配和氣流分佈進行數值模擬，給出了實現箱體流量合理分配的氣流分佈板結構調整方法和參數。
  16. The characteristics and applications of the reverse jet bag deduster, jet pulsed bag filter and electrical deduster are introduced on emphasis, meanwhile, centralized dedusting technic is recommended for vertical cement kiln plants

    其中，重點介紹了立窯反吹風清灰袋除塵器、噴吹脈沖袋除塵器和電除塵器的特點及應用，並為多臺立窯企業推薦了集中除塵的技術方法。
  17. Test method for measuring air performance characteristics of vacuum cleaner motor fan systems

    測定真空除塵器馬達風扇系統空氣特性的試驗方法
  18. Abstract : this paper introduces a new power factor meter with sample hod circuit and divider and provides basic measurment circuit. experiment result proves the practicality of the power factor meter

    文摘:本文介紹了利用采樣保持器和除法器實現的功率因數測量儀表，給出了測量電路原理圖，實驗結果表明了該測量儀表的實用性。
  19. Chapter 5 gives the design illumination of the rs coder and decoder based on fpga. then it gives the integrated results for realization design of the rs ( 31, 15 ) error - correcting code. after that, it gives the functional and layout simulation results for the limited field multiplier, divider, rs coder and rs de - coder

    第五章給出了基於fpga實現的rs編碼器和譯碼器設計說明， rs （ 31 ， 15 ）糾錯碼設計實現的綜合結果，有限域乘法器、除法器、 rs編碼器、 rs譯碼器的功能模擬和布局布線后模擬結果，最後總結主要的調試經驗。
  20. Measuring method for performance of bag filter

    袋式除塵器性能測試方法
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