驗證的處理器 的英文怎麼說

中文拼音 [yànzhèngdechǔlǐqì]
驗證的處理器 英文
validating processors
  • 驗 : 動詞1. （察看; 查考） examine; check; test 2. （產生預期的效果） prove effective; produce the expected result
  • 證 : Ⅰ動詞（證明） prove; verify; demonstrate Ⅱ名詞1 （證據） evidence; proof; testimony; witness 2 （...
  • 的 : 4次方是 The fourth power of 2 is direction
  • 處 : 處名詞1 （地方） place 2 （方面; 某一點） part; point 3 （機關或機關里一個部門） department; offi...
  • 理 : Ⅰ名詞1 （物質組織的條紋） texture; grain （in wood skin etc ） 2 （道理;事理） reason; logic; tru...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 驗證 : test and verify; checking; proving; testing; confirmation; [數學] corroboration; inspection; veri...
  1. Markup validation works like the spelling checker in a word processing program

    標記驗證的工作方式類似於字處理程序中的拼寫檢查器。
  2. In general, a precise resistor is in series with one of the resistors in wheatstone bridge to compensate the zero offset, and the other one is in parallel with another arm of the wheatstone bridge to compensate thermal zero drift. based on this principle, in this paper, a compensation method based on virtual instrument technology has been put forward. actuated by current source, a good calculation method of compensation resistors and their position in the bridge is deduced

    本文基於串並聯電阻補償法的原理，提出了一種基於虛擬儀器的誤差補償方案，推導了在恆流源供電下可以精確的計算出補償電阻大小和補償位置的演算法，並且在虛擬儀器軟體平臺labview上完成了數據採集、處理、顯示等軟體的設計，經過實驗的驗證，對傳感器的零點溫度漂移補償取得較好的效果，而對靈敏度溫度漂移的工藝補償亦有一定的效果。
  3. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  4. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  5. Experiments on the gas flow patterns in the flowmeter prove that the algorithm used in arm digital gas mass flowmeter is capable of significantly improving the sensitivity of the heat sensor, hence superior in terms of the measurement of gas mass flow

    並將此演算法應用於以arm處理器為核心的數字式氣體質量流量計中實驗證明，該方法能夠明顯改善熱式傳感器的動態響應速度，實現其快速補償。
  6. To testify the correctness of the system ' s design, three routines are designed in this thesis : 1. clock tick test ; 2. task management directives test ; 3. cpu usage test

    為了驗證系統設計的正確性，論文設計了3個驗證常式，它們是：一、時鐘滴答測試；二、基於單處理器的任務管理指令測試；三、 cpu利用率測試。
  7. In chapter 4 we discuss the design of the high speed and high performance vlsi and its imp1ementation, firstly we ana1yze and compare the features and ru1es of al1 kinds of fft algorithm, adopt complex radix 4 butterfly calcu1ation as basic alu, then discuss all kinds of process architectures, the design thoughts, rule, method, technique way, the characteristics of the design are r4 dit algorithm, pingpong ram design method and pipeline structure between stages. we also analyze the limited word length effect and the method to avoid overflow of the fixed points fft process, bring out the expandable platform mode

    第四章主要討論了高速高性能的快速傅立葉變換處理器的設計和實現，首先分析和比較了各種快速傅立葉變換演算法的特性和規律，提出基4蝶算的演算法具有最好的性價比，討論了順序、級聯、并行和陣列的處理結構，闡述了設計高速高性能快速傅立葉變換處理器時的設計原則、設計思路、所採用的技術路線，驗證並測試fft處理器，分析了定點fft處理過程由於有限字長效應所產生的量化誤差的范圍及防溢出控制辦法，提出了可擴展平臺模式。
  8. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  9. In practical studies, finally, a hybrid active power filter based on the digital signal processor ( dsp ) and intelligent power module ( ipm ) was set up, including a cycloconverter acem. based on the experimental set - up, plenty of experimental studies were conducted. the experimental results demonstrate that the self - adaptive technique, the topology of series connected hybrid power filter and the corresponding significant technologies described above are feasible and practical

    最後，實際研製了一套以dsp （高速數字信號處理器）和ipm （智能功率模塊）為核心的小功率混合型有源濾波裝置，在交交變頻acem實驗平臺上進行了全面的實驗研究，充分驗證了本文所提出的自適應同步相關濾波技術、優化混合型濾波器拓撲結構和有關的關鍵性技術的正確性和實用性，從而從理論到實踐全方位、成功地實現了對交流勵磁發電機輸出電力諧波抑制的研究。
  10. The verification process for a digital signal processor with very long instruction word ( vliw ) named thuasdsp2004, which is developed by tsinghua university microelectronic institute sponsored by national natural science foundation, is analyzed at the register - transfer level in this paper

    本文介紹在國家自然科學基金的資助下，由清華大學微電子研究所設計的具有超長指令字（ verylonginstructionword ， vliw ）體系結構特點的數字信號處理器thuasdsp2004的rtl級功能驗證工作。
  11. In this paper, the hal - c conception is studied according to the project requirements, and describes the functions of the hal - c in software waveform implementation. then the issues implementing the hal - c on the specialized hardware processor are addressed, and the methods of managing the components on fpga and dsp by proxy components with the domain descriptor file and the configuration table are brought out. in the end, the validity of the proposed methods is tested

    論文以sca體系結構驗證實現項目為背景，深入研究了sca專用硬體補充規范，重點分析了硬體抽象層連接的意義以及它在波形組件開發中的作用，提出了它在dsp / fpga上實現的方法、步驟;接著從sca波形應用的角度描述了硬體抽象層連接在波形開發中的作用，給出了代理組件如何通過域描述文件和配置表管理專用硬體處理器上演算法組件的方法;最後對dsp / fpga上的硬體抽象層連接進行了驗證性測試。
  12. All result data indicate that random test can play a very valid role in function verification of embedded processor

    所有的數據表明，隨機測試在嵌入式處理器的功能驗證中能夠起到非常有效的作用。
  13. Firstly, for the purpose of research and verification of multithread microprocessor, a superscalar microprocessor model armp - v2 is built on the basis of armp microprocessor ; secondly, the issue logic is not only the critical path in a superscalar microprocessor, but also critical to the performance of a multithreaded microprocessor with superscalar execution core

    首先，在設計的嵌入式微處理armp的基礎上進行改進，提出了一個超標量處理器模型，用於多線程處理器系統結構的研究與驗證。其次，指令發射邏輯是超標量處理器中的關鍵路徑，也是制約執行單元為超標量結構的多線程處理器主頻提高的關鍵因素。
  14. The author is absorbed in research on technology of coprocessor design. in the floating - point addition the paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading - zero logic circuits, considering algorithm and construction of logic circuits. an approach of micro program controller design for coprocessor is put forward and a test bench is given to verify its function

    筆者研究協處理器的設計技術，在浮點加法器中提出動態與靜態結合設計進位鏈的方案以及前導零預測面積與速度的折衷方法；在微程序控制器的設計中提出一種協處理器微程序控制器的設計方法，並且給出其功能驗證的測試平臺。
  15. Experiments validate that the encoder can realize real - time video coding at the speed of 25 cif pictures per second. moreover it possesses good visual quality and high compression ratio

    通過測試驗證，該編碼器在保持很好的圖像質量和高壓縮比的同時，實現了實時的視頻壓縮，處理速度可以達到cif格式的25幀/秒。
  16. In the latter part, we discuss some classical algorithms of conventional amti and stap and present a new method to combine space conventional beamformer with the maximum improve factor amti filter. then we present a concrete method of putting dpca into aerial phased array ' s amti, simulation result proves the validity

    在自適應動目標指示部分，討論了常規amti處理和空時聯合自適應處理的各種演算法，提出一種將空域常規波束形成與最大改善因子amti濾波器相結合的處理方法並進行了模擬驗證。
  17. And now we finish the step - nc file. in the process of designing post - processor, our aim is converting step - nc file to some type cnc control code, and in this way verifying the step - nc file gained from pre _ processor

    在後處理器的設計中，我們的主要目的是把step - nc文件轉換成某種類型的數控機床控制系統的數據指令，以此來驗證前處理器中得到的step - nc文件的正確性。
  18. Handles the server side of an authentication for a client - server connection

    處理客戶端/服務器連接的身份驗證的服務器端。
  19. It is proved by its performance analysis and experimental results that the utilization of processors is increased, that all processors have better load balance. therefore the efficiency of computing scalar multiplication is heightened

    其演算法性能分析和實驗結果證明:改進演算法可提高處理器的利用率，保證各處理器單元具有較好的負載均衡特性，從而加快標量乘的計算速度。
  20. Theoretical proof and simulation suggests that this constructive function has stronger heuristic power, and has better effectiveness for scheduling dag a task - replication based heuristic static scheduling algorithm is also proposed ( namely processor pre - allocation algorithm for dag tasks, ppa ), utilizing the aforementioned heuristic function aimed at rtrpmt

    通過理論證明與模擬實驗表明：本文構造的啟發函數具有較強的啟發能力，對dag圖的調度具有較優的效果。利用本文所構造的啟發函數，針對相關周期性多任務，提出了一種基於任務復制的啟發式靜態調度演算法（ dag任務圖的處理器預分配演算法ppa ） 。
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