高速內存器 的英文怎麼說

中文拼音 [gāosùnèicúnqì]
高速內存器 英文
high speed memory device
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 內 : 名詞1. （內部; 里頭; 里邊） inner; inside; within 2. （妻子或妻子的親屬） one's wife or her relatives 3. （姓氏） a surname
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  1. Vmebus boards have data bus sizes of 16, 32, or 64 bits and are designed to be plugged into a backplane that has up to 21 slots for other boards. these other boards can ben cpu boards or peripheral boards providing various functions. the vmebus standard originated with the motorola versabus in 1979 which was designed using the then new mc68000 microprocessor

    性能的提高主要是由於三個方面的改進： 1 .處理器及高速緩存性能的優化2 .降低內存瓶頸：通過對powerplus體系結構的改進，使內存性能提高到582mb s memory read bandwidth和640mb s burst write bandwidth 3 .系統總線吞吐率的優化：其他的晶元組對pci到內存帶寬只能到70mb s ， powerplus ii則能達到80mb s而無須消耗額外的cpu資源。
  2. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  3. In the optimization design of advanced router, since it exists hol blocking in iq program, and when the number of ports is large or the line rate is very high, the present memory cannot have so fast frequency in oq program, so cioq program is adopted now

    在路由器的優化設計中，由於輸入端排隊方案存在隊首堵塞且輸出端排隊方案在主幹網上存在加速過高而現有的內存頻率跟不上的弊端，所以現在採用了組合輸入輸出端排隊方案。
  4. Pipelining, superscalar organization and caches will continue to play major roles in the advancement of microprocessor technology, and if hopes are realized, parallel processing will join them

    在微處理器技術的發展中，流水線操作、超標量體系結構和高速緩沖內存儲器仍將扮演著重要的角色。如果可能，平行處理方法也會加人。
  5. To use an intermediate storage ( magnetic disc ) when making a data transfer between highspeed storage ( usually main storage ) and a device that operates at a lower speed

    當高速存儲器（通常是內存）和低速運行的（外部）設備之間進行數據傳送時，利用中間存儲器（磁盤）作緩沖（的技術或過程） 。
  6. It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks

    在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分，由於有了存儲器介面的存在，使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性，而只需關心傳輸協議和一些定義的遲滯參數，在客戶看來存儲器僅僅是一個線性的幀緩沖器，所有的換頁、區段切換都交由介面電路來處理，從而大大簡化了客戶對存儲器操作的復雜度。
  7. In the hardware design, the analog circuit, high - speed a / d convertor, storage control logic and vxibus interface are discussed. the results of the simulation and analysis of the circuits are given

    在模塊的硬體電路設計部分中，著重對信號調理電路、高速a / d轉換器、高速存儲邏輯控制以及vxi總線介面等內容進行了討論，給出了具體的電路設計和關鍵器件的說明，並對部分模擬電路和數字電路進行了模擬分析。
  8. Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture

    現代計算機和cpu設計中， cpu片內的寄存器、一級高速緩存（ level1cache ）和二級高速緩存（ level2cache ） ，主板上的三級高速緩沖，再加上主存，外存（硬盤、軟盤、電子盤等） ，構成了現代計算機的多級存儲體系結構。
  9. We analyzed the anti - jam and band inside anti - interfere performance of the system, and the low probability intercept ( lpi ) of the traditional direct sequence spread spectrum ( dsss ) modulations in the uav platform ' s applications. so a new modulation technique using a multi - level pseudo noise ( pn ) code has been presented. the new multi - level pn code is built from a high speed pn code through a low passed filter ( lpf )

    分析了系統抗阻塞式干擾和抗帶內頻帶干擾的性能，以及常規bpsk qpsk - dsss調制在無人機通信中存在的安全隱患，提出了一種用多電平pn碼進行擴頻調制的方法：採用高速pn碼，經過低通濾波器，產生多電平pn碼進行直序擴頻調制，能在低信噪比情況下有效抵抗平方率檢測器對系統載波的檢測。
  10. 2. the design of low - level driver of powerpc 405. after thoroughly collecting and consulting the latest information in the field of sopc, in this thesis we choose fpga embedded powerpc405 processor hardcore to construct the demanded sopc system, which manages to meet the application demand between

    論文課題在認真深入地調研了國內外sopc領域的最新資料后，選擇了嵌入powerpc405處理器硬核的fpga片上可編程系統，解決vxi介面與本地ram控制器的通訊和靜態存儲器存儲控制等方面的應用需求，通過powerpc硬體設計和底層驅動軟體編程，構建了滿足設計需求的高速數字測試系統。
  11. It is expected that the standard will be used for a wide range of bit rate, not just low bit rate applications and that h. 263 will replace h. 261 in many applications. to realize the real time video compression, a high performance processor is necessary

    視頻數據壓縮運算量大，需要大量的存儲空間，要實現實時的視頻數據壓縮無疑需要一個高速處理器， tms320c6711dsk是ti推出的面向圖像處理的硬體平臺，其運算速度可達到900mflops （百萬指令位元組每秒） ，可用內存達16m位元組，是進行視頻壓縮的理想平臺。
  12. Built - in high - performance single chip microcomputer and memory to guarantee high data speed processing and reliable preservation

    內置高性能單片機和存儲器，保證數據高速處理和可靠保存。
  13. In this system, it is master - slave structure between pc and dsp. dsp transfers data to pc by adopting the dmac ( direct memory access controller ) in pc. the thesis dwells on every part of hardware circuit and main technology such as dsp, the transferring mode of dma ( direct memory access ), etc subsequently, it introduces the software design of the sampling system and user interface

    該最小系統製作成高速數據採集卡，插入pc機的isa總線插槽中， pc機與dsp構成主從結構，系統中tms320f240dsp作為pc機的下位機，採用pc機內的dmac （ dma控制器）通過dma （直接存儲器存取）方式把採集的數據傳送到pc機進行處理。
  14. It contains two a / d channels, every channel has a 4kx 16bit buffer. it has three flexible trigger modes : inner trig, outer trig and software trig. vvp platform can support up to 4 plug - in boards ( 8 channel a / d ) to work together

    該模塊作為一塊vvp儀器平臺上的插板，採用20msps的16位a d轉換器，一塊插板上設計了2個高速a d轉換通道，每個通道有4k 16位的緩沖存儲器，可以內部觸發、外部觸發和軟體觸發。
  15. When its performace is determinate, the efficiency of the memory in a system depends on the design of the interface controller. this paper discuss the design of the nice interface controller from interconnection strategy selection, interface protocol establishment and memory timing parameters. sgram is one of the successful graphics device with high performance and high speed in the multimedia technology application area recently. fsm resolve the arbitration mechanism and timing matching problems in the sgram controller design

    在存儲器性能確定的情況下系統如何高效率地使用該存儲器決定於其介面控制電路設計的優劣。本文從介面策略選擇、介面協議制定以及存儲器遲滯參數入手討論如何設計性能優良的存儲器介面。 sgram是近年來出現的較為成功的面向多媒體技術的內存器件之一，是一種高性能、高速度圖像存儲器。
  16. First of all we discuss the model of information purifying and bring forward the methods of setting up the according fuzzy set and subject function. secondly after analyzing the traditional technology and the strongpoint and the shortcoing of information purifying we improve it combining with the technique of fuzzy mode identifying, data warehouse, cache etc. and we can perpetrate an on - line and synchronous purifying through analyzing the text and picture showing in the pages of network. finally, we choose sql server 2000 to design the url database and delphi, wingate as the tool for system development to develop an efficient system of information purifying which can keep the network consumer especially young student apart from the intrusion of unfriendly information and make the environment of network pure and fine

    本文首先探討了該系統中的信息「凈化」模型，提出了模型中的模糊集及隸屬函數的構造方法；然後分析了傳統的信息「凈化」技術及其優缺點，結合模糊模式識別、數據倉庫、高速緩存等技術對傳統的信息「凈化」技術進行了改進，改進后的信息「凈化」技術可通過分析正在顯示中的網頁文字、圖片內容，做即時、同步性的網頁內容篩選；最後，利用sqlserver2000設計了url數據庫，選擇delphi 、 wingate作為系統開發工摘要具，設計開發了一種高效的網路「凈化」器，使網路用戶尤其是青少年學生遠離非友善信息的侵擾，讓網路環境更加純凈、美好。
  17. Software design includes many aspects, such as design of interface, interrupt and clock control, monitoring, etc. sampling and accessing quickly data of chromatogram peak is an important tache to ensure analytic and real time performance of chromatograph, fifo make high - speed input and output of a / d sampling data possible, and expended memory, instead of disk, save a great deal of peak data and process parameter

    硬體系統由cpu 、 a / d 、 d / a 、顯示驅動、實時鐘五個模塊組成，軟體設計包括譜峰數據的高速採集和存取、人機界面的設計、中斷和實時鐘控制、監測控制等方面的工作。譜峰數據的高速採集和快速存取是保證工業色譜儀分析性能和實時性的重要環節，採用了fifo存儲器技術實現a / d采樣數據的高速輸入輸出，使用擴展內存代替硬盤存貯過程參數和海量的譜峰數據。
  18. In practice, the file system calls the kernel cache manager, which fulfills requests from an in - memory cache if possible and makes recursive calls to the file system driver to fill cache buffers

    實際上，文件系統調用內核高速緩沖存儲器管理器，這個管理器執行來自於一個內存中的高速緩沖存儲器的請求，如果可能的話，並且遞歸調用文件系統驅動來填充高速緩沖存儲器。
  19. The value of the shells inner diameter is sent into the data memory of the main controller whose core is the avr high - speed embedded single - chip microcomputer and is displayed at last

    被測炮彈內徑的測量值，最後送入以avr高速嵌入式單片機為核心的主控制器的數據存儲器中並顯示。
  20. It probes its surroundings looking for suitable peripheral devices such as displays, input devices, processors, fast access memories and access points to communication channels

    它搜索其周圍，尋找適合的外部設備，如：顯示，輸入，處理器，高速訪問內存和通訊頻道的接入點。
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