高速寄存器 的英文怎麼說

中文拼音 [gāosùjìcúnqì]
高速寄存器 英文
high eed register
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  1. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  2. Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz

    本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。
  3. Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture

    現代計算機和cpu設計中， cpu片內的寄存器、一級高速緩存（ level1cache ）和二級高速緩存（ level2cache ） ，主板上的三級高速緩沖，再加上主存，外存（硬盤、軟盤、電子盤等） ，構成了現代計算機的多級存儲體系結構。
  4. Known well vxibus criterion, the structure of configure register and vxi address mapped theory. known well the structure and work theory of high speed synchro data acquisition device

    熟悉vxi寄存器基器件的配置寄存器結構， vxi地址空間映射原理；熟悉高速同步採集卡的總體結構和工作原理。
  5. Making use of the powerful capabilities of the pci chip, high - speed data of the dsp platform are transferred both ways at dma mode, and low speed data such as initialization and configuration information are transferred at direct slave mode. this paper shows in detail the workings of pci9054, the configuration of its control register, and the writing of platform driver with api functions provided by the manufacturer

    利用pci介面晶元的強大功能，本文提出了採用dma模式雙向傳輸dsp平臺的高速數據，採用從模式傳輸初始化信息及配置信息等低速數據，並詳細介紹了pci9054的工作方式，控制寄存器的配置以及調用廠商提供的api函數編寫平臺驅動程序。
  6. From the born of microprocessor to now, register file as its key part, requires higher read and write access speed. but, along with the development of the register file directing to large - scale and multi - port, realizing a high speed design becomes a difficult problem nowadays

    微處理器誕生至今，寄存器文件作為其內核關鍵部件，往往需要很快的讀寫訪問速度;但是隨著寄存器文件向著大規模、多埠方向發展，實現高速讀寫成為了當前研究的一個難題。
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