高速邏輯 的英文怎麼說

中文拼音 [gāosùluó]
高速邏輯 英文
high speed logic
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 邏輯 : logic
  1. This paper presents the logic circuit design of ccu for lx - 1164 cpu chip, for ccu, data and instructions are stored in separate data and instruction caches

    本人有幸在夏宏博士的指導下參加這一工程，承擔lx ? 1164cpu的高速緩存控制器（ ccu ）的邏輯設計和功能模擬。
  2. These character based on sichuan power network ' s practice operation experience, in allusion to the config of the carrier wave protection in bypass breaker operating, through the study of protection ' s typical config : one side lfp - 902a, one side csl - 101a, proceeded comprehensive act module test, noted plenty of first hand test data and wave picture, proceeded detailed theory analyses, plenitude demonstration atresic type carrier wave distance protection when twain side atresic type logic is not completely same, basically can fill power network ' s requirement to relay of reliability selectivity speedly and sensitively

    本文結合四川電網的實際運行經驗，針對旁路開關代路運行時的保護配置情況，通過對旁路代路時保護典型配對組合：一側lfp - 902a ，一側csl - 101a的保護配置情況的深入研究，做了全面的動模試驗，記錄了大量的第一手試驗數據和波形，進行了詳細的原理分析，充分驗證了高頻閉鎖式距離零序保護在兩側閉鎖式邏輯不盡一致的情況下，基本能夠滿足電網對繼電保護的可靠性、選擇性、快速性以及靈敏性的要求。
  3. Through the simulation of large - scale circuit simulation proved that use the crossover tearing technology could detailed network structure, simplify the diagnostic process, and the neural network can parallel deal with the diagnosis information, and the logic operation can judge the information of the multi - fault. the illustrative simulation shows that it can increase the diagnosis speed and decrease the workload before test

    通過對大規模模擬電路的模擬證明，使用交叉撕裂明細網路結構，簡化診斷過程，且運用神經網路組對信息進行并行處理，邏輯分析運算對多故障信息進行處理判斷，大大提高了故障診斷速度，減小了測前工作量。
  4. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  5. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。
  6. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  7. The high - speed data buffer is designed by adopting cpld and general high - speed static memory. 5

    採用cpld控制邏輯外加通用靜態高速存儲器來實現採集后數據的高速緩存。
  8. In this way, the cost of semi - active method will be cut and the damper was easy to be maintain

    該方法簡單、方便、有效，能適應高速列車運行時對橫向減振力控制邏輯的要求。
  9. This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed

    本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。
  10. Chapter three is about the experimental research of the real time optimal position system ( see chapter two ), emphasis on the high performances of 196mx pts interrupt response and safe design of ipm module. the analysis of perfect experimental waveforms and basic algorithm are also provided. chapter four focus on the properties and application of ekf estimator

    論文第三章對點對點快速定位系統進行了實驗研究，重點介紹了196mxpts中斷系統對高速處理實時邏輯信號和消除編碼盤光電頭邊緣振蕩效應所起的作用、 ipm模塊的安全性分析設計等，同時給出了完整的實驗波形分析以及基本演算法。
  11. And, the thesis mainly presents the research on the key technique of the dataflow control, including the realization of the pci interface control, the control of the sram memory that read or written by fpga, the pretreatment and the output control of the image and the intercommunication between pc and fpga. and then, it presents the design and the realization of the pc application program. in the end, it presents the debugging stepps and the application of the system.

    本文的重點在於介紹高解析度實時圖像處理系統的fpga控制邏輯設計，主要研究了該數字圖像處理系統中影響系統實時處理速度的數據流控制技術，如pci介面控制、 fpga與外部ram的高速讀寫控制、圖像的採集預處理，圖像的輸出控制等，本文還介紹了高解析度實時圖像處理卡的上位機應用程序設計與實現，本文的最後介紹了系統的調試及應用。
  12. This work is focused on the research of the real time response 、 transplantable 、 reducible and configurable of the file system

    Deltafile文件系統分為三個實現層次，分別是:虛擬文件系統、邏輯文件系統和塊高速緩存。
  13. The implementation of deltafile 3. 0 can be divided into two modules ? real - time file system module and manage module for both facilities and drives. the real - time file system contains four parts ? system call api layer, file node manage layer, virtual file system layer, concrete file system layer, which perform the abstraction of the facility

    實時文件系統模塊包含系統調用api層、文件節點管理層、虛擬文件系統層、具體邏輯文件系統層四部分，主要完成與設備無關的數據存取介面抽象和各種文件系統標準的實現;設備與驅動管理模塊包含邏輯設備管理層、物理設備管理層、設備緩沖區高速緩存層、設備驅動管理層四部分，主要完成外部存儲設備管理及其驅動介面抽象功能。
  14. 2. the high performance realization rules and experiences are discussed at the level of micro - architecture, logic and layout respectively

    2 ）分別在結構級，邏輯級和版圖級分析了高速數字電路的高速解決方案。
  15. The hardware of the system is composed of a high - speed optical - isolator circuit, a first - in / first - out dual - port memory buffer circuit, a pci interface chip ql5032, and a logic control circuit

    系統的硬體部分是由高速光電隔離電路，雙埠fifo存儲緩沖電路， pci總線介面電路ql5032及邏輯控制電路等組成。
  16. As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost

    所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。
  17. 4. complete the design of system ’ s logic function with fpga. the sdram ’ s controller and ping - pong operation is studied, and the data ’ s continuous storage is also realized. 5

    4 .設計實現系統的fpga邏輯部分，並研究了高速大容量sdram控制器和進行乒乓存儲操作邏輯時序，實現了數據流的連續傳輸。
  18. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  19. Very high speed logic

    超高速邏輯
  20. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
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