buffer scheduling 中文意思是什麼

buffer scheduling 解釋
緩沖調度
  • buffer : n 1 【機械工程】緩沖器，緩沖墊；阻尼器，減震器；消聲器。2 【化學】緩沖，緩沖劑。3 緩沖者；緩沖物...
  • scheduling : 編排；調度
  1. In this dissertation the ts demultiplex task and ac - 3 decoding task in mpeg - 2 protocol are scheduled by 2 policies. one is the buffer - drive policy and the other is deadline - drive policy. some experiments have been done to confirm the policy and the arguments of the scheduling

    本文根據hdtv信源集成解碼晶元的工作原理，對mpeg - 2協議中的ts流解復用任務和ac - 3音頻解碼任務提出緩存驅動和時限驅動兩種調度策略。
  2. The different scheduling characteristics of three production types - continuous production, discrete production and mixed production are first described, a solution is proposed that uses buffer to adjust the characteristics of mixed production, and a scheduling model that combines mrp and opt is presented according to the production requirement of fuda co. in chapter three, the production order ( similar to mps ), mrp and crp in the scheduling are discussed in detail

    第二章是混合型生產計劃調度特點，首先分析了三種類型生產過程（離散型、連續型和混合型）的特點，進而討論了混合型生產計劃調度的特殊要求，提出在混合型生產過程中利用緩沖區來實現離散型生產和連續型生產的平穩過渡。在此基礎上結合富達公司的實際生產情況提出了集成mrp和opt思想的混合型生產控制模型。
  3. Because of block in head of line ( hol ), input buffer strategy make the whole switch system performances declining drastically at heavy oflbred load, and some improvements of input buffer strategy are put forward to overcoming tlle head of line block. virtual output queues ( voq ) is chosen as input buffer strategy. dpa and ilqf ce1l scheduling algorithms for voq are silllulated

    由於輸入緩存的隊頭阻塞使得高負載條件下輸入緩存策略的交換系統各方面性能急劇下降，由此提出了克服輸入緩存隊頭阻塞的改進方法，最後本文決定選用虛擬輸出隊列（ voq ）的輸入緩存策略，並且研究了與虛擬輸出隊列相對應的ilqf （最長隊列優先）和dpa （對角線優先）信元調度演算法，為交換系統的asic設計提供依據。
  4. Stability analysis of buffer priority scheduling policies using timed petri net models

    網模型的緩沖優先調度策略穩定性分析
  5. We analysis the conflict, convert channel and starvation problems of concurrent schedule based on strict - 2pl locking protocal which applies nhstm model, then present a concurrent scheduling algorithm making use of buffer and point p. also, we proved the concurrent schedule algorithm is serializable. at the same time, we introduce the key technical used in nhsdb concurrency control mechanism, and give the implementation details

    我們對應用nhstm模型的，通過應用嚴格兩段鎖協議實施的並發調度中，可能存在的並發沖突，隱通道和饑餓問題進行分析，在此基礎上提出了一種利用緩沖和p點的並發調度演算法，並給出了該演算法的並發調度正確性證明，解決多級安全條件下的隱通道和饑餓問題。
  6. 3 ) design switch system using eda based on the result of a11alysis. because the function of switch system is very complicated, some modules are designed by schematics directly, most modules are designed by verilog hdl using eda technology, synthesized by the synopsys software. at last a high speed atm switch system is designed, including voq as input buffer strategy dpa cell scheduling algorithm and crossbar switch fabric

    在前面分析的基礎上根據目前的條件，對一個空分交換系統各模塊進行前端設計和模擬，由於交換系統的功能復雜，我們一部分將採用直接畫原理圖的方法進行設計，大部分將採用集成電路設計自動化的方法進行設計，即採用硬體設計語言verilog ? hdl進行設計，用synopsys軟體對設計進行綜合，生成線路圖，然後作門級電路模擬。
  7. Quite a lot of new ideas for designing both logic structure and scheduling structure of the open architecture cnc system have been implemented, including the principles of module - classification, large buffer mechanism for data transfer between modules, principles of time - allocation scheduling, and etc. based on the software structure, the author implemented a few function - modules, such as master - control, interface, decode, interpolation, position - control

    本文在系統的邏輯架構設計和時序架構設計方面做了不少創新性的工作：提出了開放式數控系統的模塊劃分原則，設計並實現了模塊間的大緩沖機制；提出了開放式數控系統的時序設計原則，提出了rtlinux環境中的數控系統時序實現機制並給出了具體方案。
  8. Two 3 - frames - grained scheduling policies are suggested to make good trade - off between processing demands and on - chip buffer demands in software decoding implementation. a static time division multiplexed scheduling / dynamic fixed priority arbitration based 2 - level hybrid arbitration scheme, incorporated with synchronization control, is introduced in this paper to utilize the bus bandwidth effectively and lower on - chip buffer demands in media soc

    提出了一種基於靜態分時復用調度動態固定優先級仲裁的混合二級總線仲裁策略，通過分割總線時間片靜態調度媒體數據流dma傳輸，使之與解碼流程同步配合，有效地分配和使用總線帶寬，降低了片上數據緩存等硬體開銷。
  9. We can ration analyze and estimate hardware configure chosen in design such as machine tool, the capacity of buffer, the route of transport system etc, and personnel deployment of product line. we can forecast the produce cycle of product, analyze and forecast produce capacity of work - flow, simulate all kinds of predictable or random malfunction, finding bottleneck of system etc. we can also forecast the capability of work - flow under different scheduling strategy

    通過對流水線的模擬，我們可以對各種設計方案進行評估，可以定量分析與評價設計中所確定的硬體配置（如機床、緩沖庫容量、運輸系統路徑等）及生產線人員配備情況，預測產品生產周期，分析與預測生產線的生產能力，模擬各種可預見的或隨機的故障，發現系統瓶頸等。
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