bus clock 中文意思是什麼

bus clock 解釋
總線時鐘，總線定時
  • bus : n （pl busses buses）1 公共馬車；公共汽車；客機。2 〈口語〉汽車，機器腳踏車；飛機。3 【電學】信息...
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  2. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  3. 3. with time series simulation software, the cpu ’ s i / o ports simulate i2c bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices

    3 、採用軟體模擬時序使cpu的i / o口模擬i2c總線，實現了單片機與時鐘晶元、溫濕度傳感器、存儲晶元等器件的數據交換。
  4. A 16 - bit risc microprocessor soft core is designed, and the instruction system, controller, bus and clock are studied

    本文設計了一個16位精簡指令集微處理器軟核16rmpu ，主要研究微處理器的指令系統、控制器、總線和時鐘等設計。
  5. The host has ultimate control over the bus and may inhibit communication at any time by pulling the clock line low

    主機對總線有最高的控制權，在任何時候通過將時鐘線拉低就可以禁止通信。
  6. In order to improve reliability and simplify the hardware design, many new i2c bus elements were used to realize binary input, logic output, clock functions and storing settings and reports. by simulating i2c bus data transfer, the mcu realized writing and reading data from each element the whole hardware system ' s structure is compact and reasonable, and the device has high reliability, stability and immunity to disturbance

    從提高可靠性和簡化電路的角度出發，設計硬體電路板時使用了許多新型i ~ 2c串列介面器件， mcu用普通i / o口模擬i ~ 2c總線介面，由軟體模擬i ~ 2c總線數據傳輸過程，實現了開入開出、定值存儲、報告存儲和時鐘對時等功能。
  7. At the same time the clock chip pcf8563 and serial eeprom chip csi24c01 with reset and wdt circuit of i2c bus are used hi the system. they have not only provided the non - volatility data storage area, the supervision ability of power supply and mcu and the rtc, and its i2c bus structure has been simplified the circuit design

    同時在系統中還使用了護c總線結構的時鐘晶元pcf8563和內置reset 、 wdt電路的串列eeprom晶元csi24coi ，它們不僅提供了電源和微控制器的監控功能、不揮發性的數據存儲區、實時時鐘，而且其護c總線結構簡化了電路設計。
  8. Bus clock rate

    匯流排時鐘頻率
  9. The peripheral equipment, which includes serial control, b3g test tools, ddr control, interrupt control, connect the on - chip peripheral bus of powerpc ~ ( tm ) 405. in addition, the clock module and the misc logic module are necessarily to make the b3g test platform work. in order to debug the b3g test platform, the chipscope ~ ( tm ) core is adopted

    在powerpc ~ （ tm ） 405的外圍總線上開發了串口控制器、 b3g測試工具、雙倍數據流（ ddr ）內存控制器、中斷控制器等外設;整個系統還需要時鐘、輔助邏輯等模塊;為了方便b3g測試平臺的調試，將chipscope ~ （ tm ）核也嵌入到了平臺中。
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