bus interface level 中文意思是什麼
bus interface level
解釋
總線介面電平-
Its principle is as following : acquire and modulate the analog signals from sensors placed in environments through daq device on real time, then transit the information to computers by pci bus ; in the other hand, noise information tested with sound level meter is passed through interface rs - 232 to computers
本系統工作原理為：通過多功能數據採集卡採集來自各種傳感器所採集的各檢測對象的模擬信號，對信號進行調理，通過pci系統總線傳遞給計算機；而噪聲則通過聲級計由rs - 232傳入計算機。 -
According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system
針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。 -
Becausc of using the advanced dsp, popu1ar high speed pci bus and laxge scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree
由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得本設計的整個系統具有相當的水平。 -
Because of using the advanced dsp, popular high speed pci bus and large scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree
由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得整個系統具有相當高的數據處理能力。 -
Bbl back - side bus logic. logic for interface to the back - side bus for accesses to the internal unified level two processor cache
後端總線邏輯。訪問內部統一二級處理器緩存的後端總線介面邏輯。
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