cache block 中文意思是什麼
cache block
解釋
超速緩存塊-
Through the implementing of kernel level file and cache mechanism at the client side, this newly proposed distributed network file system provides seamless network file access and reduces the performance decline caused by network transmission. utilizing the concept of logic block server, it provides the reliable data block storage and implements redundant storage capacity. utilizing the concept of the index server, it provide s the cost of the greatly for server and network during data access process and realizes the computing with balancing capacity
在客戶端通過實現內核級文件的調用和緩沖機制，實現了文件的無縫網路存取，並減少由於網路傳輸帶來的性能下降的影響；利用邏輯塊服務器實現邏輯塊的冗餘存取，實現數據塊的安全存放；利用索引服務器進行負載均衡計算，實現資料存取的較低網路和服務器開銷；利用索引服務器實現服務器組的零管理，使該系統具有高效性、穩定性和可伸縮性。 -
In the mean time, the block will also be copied into the cache for future reference
在平均時中，區段也將會進入隱藏所之內被復印作為將來的叄考。 -
When a thread exits a synchronized block as part of releasing the associated monitor, the jmm requires that the local processor cache be flushed to main memory
當線程為釋放相關監視器而退出一個同步塊時， jmm要求本地處理器緩沖刷新到主存中。 -
Direct file system access, a provision that allowing a migrated process to directly access files in the current loaction, is supported by mosix through the mosix file system ( mfs ). to make dfsa work, a single - node consistency is required, and mfs can support the requirement by caching the only block data on the file server in the cluster system, but the traditional linux cache mechanism on the file server ca n ' t provide enough buffer caches to both the local and the remote client processes
機群文件系統提供的文件訪問效率對整個機群系統的性能有著至關重要的影響， mosix負載均衡機群系統利用搶占式進程遷移和直接文件系統訪問（ dfsa ）機制，實現了機群節點間的負載均衡和資源的協調使用， mosix機群文件系統mfs通過在服務器節點進行全局唯一的緩存實現了單一節點一致性，提供了對dfsa機制的支持。 -
Ad pages popup windows very waste your network width, netspeeder2 help you to block them. " web accelerator " function will download automatically the predefined pages to ie cache
而且它還可以幫助你關閉一些浪費網路帶寬的廣告頁面，查看當前正在連接的站點，以及預先下載一個你設定的網頁到緩沖中。 -
If you would like accelerate to browse your web pages, you can use the " web accelerator " function. netspeeder2 will help you cache it to ie cache before you browse the web pages. " block ads " function can block popup window, block the flying ads and block all images and flashes
現在很多網站都會彈出廣告頁，這很浪費我們寶貴的網路帶寬，網路狂飆2可以將這個網路廣告頁面關閉，節省你的網路帶寬，如果你想讓某個窗口彈出，你只要按住ctrl鍵就可以彈出，並自動錄入到網路狂飆2的白名單中，下次打開時，將會自動讓這些廣告窗口通過。 -
The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed
指令讀取器產生讀取位址以供快取記憶體讀取快取區塊內的指令。 -
In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same
分支目標緩沖器會查出是否有預測會發生的分支指令跨過多個快取區塊，則讀取位址會指到下一個快取區塊而搜尋位址則會保持不變。 -
This cache is invalidated during when the resource is deleted or relocated, and when the resource state private shared, the resource owner, externalization, internalization, or role block is modified
在刪除或重定向資源和修改資源狀態（私有/共享） 、資源所有者、外化、內化或角色塊時，這種緩存是無效的。 -
This cache gets invalidated during resource deletion, parent change of the resource, modification of the resource state private shared, modification of the resource owner, externalization, internalization, and role block change
在刪除資源、更改資源的父級、修改資源狀態（私有/共享） 、修改資源的所有者、外化、內化和更改角色塊的過程中，這種緩存是無效的。 -
And hardware / software coverification is carried out to guarantee the correctness of design. in the design of hardware of memory system, according to the system specification, we select the appropriate memory capacity, sram block, associativity and the placement of cache in the pipeline
在存儲系統的硬體設計中，始終以性能指標作為依據，克服了存儲器容量、庫單元規格選擇、聯合度的選擇和cache在流水線中的位置選擇等困難，設計出了符合指標要求的指令存儲系統。 -
Also, the relactions between the best block size for matrix transpose and the size and associativity of the processor ' s cache is formulized. for parallel optimization, several programming models available on a numa system, such as lightweight processes ( sproc ), posix threads, openmp and mpi, are compared, and their speedup and coding complexity are analyzed
對于sar成像處理的并行優化，本文對比了在numa架構上可用的幾種并行編程模型：輕量級進程、 posix線程、 openmp和mpi ，針對numa架構和sar成像處理的特點從加速比、編程復雜度等多個方面進行了討論。
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