chip clock 中文意思是什麼

chip clock 解釋
其速度較慢
  • chip : n 1 碎片，削片，薄片；碎屑；薄木片；無價值的東西。2 （陶器等的）缺損（處）。3 （賭博用）籌碼；〈p...
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  1. Using domestic strained integrated resistor as weighing sensor, at89c52 single chip as control unit, combined with arithmetical magnification, analogtodigital conversion ( a / d ), real time clock, liquid crystal display ( lcd ), and series communication interface, a minitype automatic weighing lysimeter is developed. that made measurement of evapotranspiration become conveniently and effectively in studying on water use of crops

    為了方便、有效地測定植物的蒸散，為水分利用研究提供價廉物美、簡單易用的儀器，本研究利用國產的集成電阻應變式稱重傳感器，採用at89c52單片機作為控制單元，結合運算放大、模數轉換、實時時鐘、液晶顯示、數據存儲、串列通信等外圍介面電路，研製了小型自動稱重式蒸散儀。
  2. Application of real - time clock chip in real - time monitoring system

    實時時鐘晶元在實時監控系統中的應用
  3. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  4. The displaying system of calenda amp; amp; clock based on cpld chip

    晶元控制的日歷時鐘顯示系統
  5. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  6. Cryptogrammic chip introduced in this paper has been tested on the altera ' s apex20ke fpga. the main clock frequency reached 40mhz. the chip includes 30, 000 les. in order to utilize esb resource in altera ' s chip, we adopted embedded rom and ram and can realize the function of whole system with only one chip. lt is the embodiment of methodology and notion of sopc ( system on a programmable chip ). the simulation of this cryptogrammic chip proves the correctness of function of the chip, which shows that the important ideology based reconfigurable architecture has special significance in designing of cryptogrammic chip

    本文所闡述的密碼晶元在altera公司的apex20kefpga上進行了測試。工作頻率達到了40mhz ，佔用了3萬個le . ，利用altera器件的esb資源，採用內置ram和內置rom設計方法，用一片晶元即可實現整個系統的功能，充分體現了sopc的設計方法和理念，對晶元的模擬和測試均證明晶元功能正確，表明基於可重組體系結構這一重要思想在密碼晶元設計中具有特殊的意義。該晶元的設計遵循hdl設計方法學的一般方法。
  7. Increasing the window size and the issue width to extract more ilp may hinder from achieving high clock speed, limiting over - all performance, especially for the forthcoming billion - transistor per - chip era

    在這種情況下，再增加動態指令窗口的體積和發射寬度將無助於高主頻的實現，難以開發更高的ilp ，獲得整體性能的提升。
  8. The current models have phased out the g3 but continue to use the similar g4, both 32 - bit chips, running at various clock speeds ; the recently introduced g5 is a 64 - bit ibm chip that mostly adds some multimedia - specialized instructions to the power4 chip models

    當前的g3型已經逐步被淘汰，取而代之的是類似的g4型，它們都是32位晶元，運行於不同的時鐘脈沖速度下；最近推出的g5是一款64位ibm晶元，主要是向power4型晶元中添加了一些多媒體專用指令。
  9. As is known to all, the former pcb system uses an out - chip oscillator, which is called out - chip clock generator, to provide system with clocks

    比如以前的板極系統多數使用電路板上的外部振蕩電路作為系統的時鐘發生器。
  10. It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation

    並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。
  11. In the hardware designing, the system uses the lower electronic - consuming pic16f877 single - chip computer, combined with micro - work consuming design of other parts. we also used a real time clock, which is combined with the flow of liquid, so we can make inquiry the flow data conveniently

    在系統硬體設計中，採用了耗電少的pic16f877單片機，各部分採用微功耗設計，並引入日歷時鐘，將日歷時鐘和流體的流量結合在一起，便於流量數據的查詢。
  12. In the designed hardware, at89c51 single chip computer and many kinds of new type circuit chip ( including : special power measuring chip - cs5460a, ds1302 calendar / clock chip, sms0601 lcd, x5045 serial memory ) are used for design. the hardware circuit is simplified, the meter ' s anti - interference ability is enhanced and the precision of measurement is also advanced

    設計中以at89c51單片機為核心，採用多種新型集成電路晶元（包括電能計量專用晶元cs5460a 、 ds1302日歷時鐘晶元、 sms0601液晶顯示器、 x5045串列存儲器）進行介面設計，簡化了硬體電路，提高了電能表的抗干擾能力和測量精度。
  13. As the semiconductor process technology steps into the deep sub - micro scale, the increasing number of transistors on single chip is making the digital system ever more complicated, and the clock frequency has already achieved the level of kilomega hz

    隨著半導體工藝水平步入深亞微米階段，單個晶元上的晶體管數越來越多，現代數字系統變得越來越復雜，時鐘頻率也己經能達到千兆赫茲以上。
  14. The clock control da chip of mb40978 converts rgb digital vedio singal into amplitude - modulated rgb pulse that is magnified and inner - modulate laser

    經過處理的rgb視頻數字信號經過時鐘控制的da轉換和一級驅動，產生調幅脈沖信號，實現半導體激光器的內調制。
  15. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  16. If no measures are taken, the serious basic - line - shift as well as the loss of chip clock and the difficulty of the data recovery will be introduced in the optical receiver, which causes the communication to go along abnormally

    如果不採取任何措施，會給光接收機帶來嚴重的基線漂移，同時會引起碼時鐘丟失和碼元恢復困難等一系列問題，導致通信無法正常進行。
  17. 4. through using the concept of logic balance, a high performance telecommunication switch network test chip is accomplished by using xilinx virtex 300e - 6 and the working clock frequency is up to 125mhz. this chip can give an exact test for the network delay time, throughput, network delay time dither, rate of errors and lost data

    4 ）結合邏輯平衡的思想，採用xilinxvirtex300e - 6器件，為一家著名的通訊技術有限公司設計了速度達125mhz的交換網測試晶元，能夠對交換網的吞吐率，網路延時，網路延時抖動，數據包錯誤率，包丟失率等進行嚴格的測試，並根據當前網路的流量大小自動調節網路負載。
  18. In its digital processing circuit, clock chip with high precision and temperature compensation is uesd as reference clock. high frequency reversible counter is used to count trimmed impulse signal forward or backward and two pathes saw signals are selected timely by multichannel selector

    數字信號處理電路採用高精度、具有溫度補償的時鐘晶元作為基準時鐘，採用高頻可逆計數器對整形后的脈沖信號進行正向或逆向計數，採用高性能的多路選擇器控制兩路saw信號的定時選擇。
  19. However in soc or high performance cpu an in - chip high quality clock is required to guarantee the timing of all chips

    而soc或者高端的cpu一般都採用同步的數字電路設計，時鐘是整個晶元時序的保證。
  20. The implementation of in - chip clock generator is often based on modern cmos ic process technology which is usually adopted by very large scale digital system. while designing a deep sub - micrometer cmos circuit, delay, power consumption and die size are of the main factors that must be considered

    使用現代深亞微米cmos集成電路工藝製造的內部時鐘發生器要綜合考慮延時、功耗、面積等各種重要因素，而且經常要針對soc系統的需求設計特殊的電路結構。
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