chip level 中文意思是什麼
chip level
解釋
小片級-
Physical equipment as opposed to programs, procedures, rules, and associated documentation ; chip level solutions that hook onto back plane of computer to protect it
與程序、過程、規則和相關文件相對的物理設備；固定於計算機背板上的晶元保護裝置。 -
Detail specification for electronic components. multilayer ceramic chip capacitors, type ct41. assessment level e
電子元器件詳細規范. ct41型多層片狀瓷介電容器.評定水平e -
Detail specification for electronic components. multilayer ceramic chip capacitors, type cc41. assessment level e
電子元器件詳細規范. cc41型多層片狀瓷介電容器.評定水平e -
The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。 -
This thesis researched the time synchronization method for 2d - ss system, and deeply discussed the bit error rate ( ber ) performance of multicarrier domain spread spectrum chip - level differential detection ( mc - ss - cldd ) in the presence of multi - user interference
本論文從多載波擴頻通信系統出發，提出了廣義二維擴頻系統的同步演算法，並對多載波頻域擴頻碼片級差分檢測技術在多用戶情況下的系統性能進行了深入的研究。 -
Electromotor joins with high efficiency selected water pump, scm ( single chip micyoco ) control system commands water pump according to cooling water temperature which substitutes traditional strap - driving mechanism pump and forms tael - level intellectualized control cooling system combining with electromotion control of cooling fan. consequently it realizes that water pump and fan autoregulate with engine working status and assures t hat cooling water temperature keeps in the best range all the time and advances the reliability of engine working and realizes exact control of cooling water temperature in deed
選用高效率水泵與電機聯接，改由單片機控制系統根據冷卻水溫控制水泵的工作，代替傳統的皮帶帶動的機械水泵，結合冷卻風扇的電動控制形成兩級智能化控制的冷卻系統，從而，實現了水泵和風扇轉速隨發動機工況變化的自動調節，真正實現了冷卻水溫的精確控制，保證了冷卻水溫始終保持在最佳范圍內，大量減少傳熱損失降低油耗，並提高了發動機工作的可靠性。 -
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
Ultrathin wafer level chip size package technology
超薄型圓片級晶元尺寸封裝技術 -
Highest level of high - productivity in the industry, 0. 06s chip 60000cph. easy, high - efficiency, and time - saving preparation, and capability to support parts flexibly
高生產能力：實現產能為60000 cph的高速系統升級后能夠達到66000cph -
As dispatches from foreign news agencies report, toshiba now development has made a kind of every unit may stock the multilayer level chip design of two bit informations, and before it is this, every unit can only have a bit information
據外電報道，東芝日前開發出了一種每個單元可存儲兩個比特信息的多層級晶元設計，而在此之前每個單元只能存在一個比特信息。 -
It must be appreciated and accepted in telecom market, due to its advanced technology reliable performance and high cost performance. a series of technical key problems have been solved, mainly f an overal exhaustive design of the 128k switching network system was presented based on 4k net - chips, with our own intellectual property a 3 level 64k switching net was successfully designed, in which the tlevel consists of l6 4k net - chips and the s - level consists of a self designed single vlsi fpga chip with 560 pins. an optical net interface and an optical multiplexer were designed to carry out the voice transmission and distribution of l28, 000 users
在研究開發過程中，解決了一系列的技術關鍵問題，主要有：提出了基於有自主知識產權的4k網片的128k網路系統的總體設計方案；研究設計了tst三級結構64k交換網，其中t級含有16片4k網片， s級由自行設計的、 560pins的、單片大規模fpga實現；研究設計了雙機雙網雙余度的通信控制處理器系統，實現了對用戶呼叫、 tst各級網路的控制、報警等各種功能；研究設計了光網介面oni和光復用器omux ，實現了12 . 8萬用戶話音的傳輸分配。 -
According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system
針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。 -
Then a comparison is made according to their characters and the application scope of each method is determinate. from that we get the whole scheme of design for testability of dspc50, which is using boundary scan to improve the board - level testability of the chip and using full - scan in designing the nuclear circuit to reduce the difficulty of testing the chip
在此基礎上得到dspc50的可測性設計的整體方案，即採用邊緣掃描設計提高晶元在板級的可測性，同時用全掃描思想設計晶元核心電路，以降低晶元本身測試的難度，即將晶元的全掃描設計包含入邊緣掃描系統。 -
It works at high frequency with a selectable pin outside ; the working frequency is fixed at 640k / 1. 2mhz. so far as the output signal of the single - chip ic is concerned, the maximum time proportion of its high level is 88 percent, but the minimum one is 10 percent
該控制器為pwm脈沖寬度調制方式;電路正常工作溫度范圍為- 20oc 85oc ;工作開關頻率根據外圍電路輸出電壓需要為640k / 1 . 2mhz可選;輸出信號的最大占空比為90 % ，最小占空比為10 % ，晶元主要應用於lcd電壓電源管理設備。 -
This system use the floater style sensor, mechanical encoder to get water - level signal, and use the at89c51 single chip system to transform the signal into water - level data, use modem through pstn to transmit data for a long - distance, and designed a information management software system hi the irrigation works bureau information center for communication and data management. the structure of the system was discussed in the thesis
該系統使用浮子式傳感器、機械式編碼器獲取水位信號，利用at89c51單片機系統採集水位數據（簡稱：下位機系統） ，採用數據機、通過公共電話網（ pstn ）遠程傳輸數據，並在泰興市水務局信息中心通過主控計算機（簡稱：上位機）進行通信及信息系統管理。 -
Considering the disadvantages of these methods in dealing with fast fading channels, a chip - level adaptive channel estimation method is proposed in this thesis and has better performance than other methods. furthermore, a procedure to derive optimum step length for this technique is given in particular
在分別對簡單平均， wmsa和fbprelms通道估計演算法進行分析后，著重介紹了適于低速與高速衰落情況下，進行碼片級自適應變步長lms通道估計的由來、原理與實施的具體方法，並且推導了變步長的選取。 -
A chip - level channel estimation technique with varing step size is brought forward to improve the performance of rake receiver for wcdma downlink. for the first place, the effects of different channel parameters for wcdma downlink channel estimation are analyzed
通道估計是rake接收機的關鍵技術，其目的是獲得不同多徑通道的參數估計值，估計出移動通道的衰落沖激響應，能夠提高rake接收的性能。 -
As examples of vfg, this paper introduces in detail the system - and chip - level vfg of electronic devices
作為虛擬特徵生成實例，本文以電子設備概念設計為例，詳細介紹了系統級和晶元級的虛擬特徵生成方法。 -
For the training of professional system, the identification of suppliers, and the practical project, sv has the professional project engineers advanced in the av technique in china, who can offer blue print of design, installation, training and the maintenance of chip level
專業系統的培訓與廠商認證及豐富的實際工程經驗，索訊擁有國內最早從事av技術的工程技術人員，能夠為客戶提供方案設計、安裝、培訓與晶元級維修 -
Similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells. however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard - cell. because the router cannot impose the characteristic of the transistors in the standard - cell, it may reduce the performance of the whole chip
通常，基於標準單元布圖模式將版圖綜合劃分成單元內與單元間兩個層次，以簡化晶元級自動版圖綜合問題的復雜性；但隨著晶元規模的不斷擴大，基於主要以手工定製的小規模標準單元，晶元級版圖綜合問題的復雜性不斷增大，且標準單元間布線無法充分利用單元內晶體管特徵，影響晶元的整體性能。
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