clock control system 中文意思是什麼
clock control system
解釋
時鐘控制系統-
This paper introduces working principle of tower clock control system in detail from two aspects of hardware and software. some effective anti - disturb measures adopted in design process are explained
從硬體和軟體兩個方面詳細介紹了塔鐘控制系統的工作原理，並闡述了設計中所採取的一些有效的抗干擾措施 -
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
In this paper, a clock recovery system that based on phase control technology is studied
本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。 -
Realization of digital clock control system by complex programmable logic device
實現的數字鐘控系統 -
Secondly, based on the function requirement of usb device controller the system was divided into five modules, clock extracting, event detect, physical layer interface, media access controller, endpoint control layer and every module was designed in detail
其次，針對usb設備控制器的功能要求，將系統分為時鐘提取、事件檢測、物理層、介質訪問層、端點控制層五個模塊並對每個模塊進行了詳細設計。 -
Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail
基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。 -
The adm system mainly includes a oscillator, a clock generator, an amplifier, a pre - amplif ier, a comparator, an agc ( automatic gain control ), an adm analyzer & synthesizer, a d / a converter and a lowpass filter
整個系統包括：內置振蕩器，時鐘產生器，放大器，前置運算放大器，比較器， agc （自動增益控制器） ， adm分析綜合器，數模轉換器以及低通濾波器。 -
And a kind of 16 - step automatic selective programmable amplifying circuit is designed in volume resistivity measuring circuit, so as to handle sampling little and broad signal. the control and disposal system with the core of microchip at89c55wd is analyzed on chapter 4. main function unit such as the interface circuit of lcd display and keyboard, the interface circuit of micro - printer, real time clock ds12c887, and hardware anti - jamming technique are discussed
本文還設計了以at89c55wd單片機為核心的控制處理系統的外圍介面電路及其軟體，對主要功能部分進行了分析，主要包括：鍵盤液晶顯示介面及界面設計、微型印表機介面、實時日歷時鐘晶元ds12c887 、單片機與單片機及單片機與上位機的通信設計以及控制系統硬體抗干擾措施等。 -
The host computer system ' s functions are as follows : duplex communicate with automatic station data poll gather to each automatic station save and handle the data format and print diagram based on the gathered data download the parameter to automatic station and adjust the clock dial - up to network and long - distance control automatic rainfall station consists of outer garment, meet rain bucket, water input and output electromagnetic valve, measure bucket, storage battery and circuit control
可以與自動站進行雙向通訊，完成對各個自動站數據輪詢採集並進行存儲、處理，並生成圖表，根據採集的數據形成圖表、列印，可以向自動雨量下載參數、時鐘校準以及遠程聯網撥號和控制。自動雨量站包括外罩、接雨桶、進放水電磁閥、測量桶、蓄電池以及電控部分等部分組成。 -
This design is the first solid - state memory system for satellite, which can confront with multi - clock sources and multi - data sources compatibly. it is the fist design that integrates all functions of data processing and control into a single programed logic device. this design can be an ip core that can bring large advantage when system upgrade in the future
本星載固存系統是我國星載固存系統中第一個採用多數據源，多時鐘源進行兼容設計的單一固存系統；第一個採用ip化、參數化設計思想，採用單一邏輯編程器件做為固存系統唯一控制部件，為以後系統升級帶來了很大好處；第一個採用功耗均衡思想來降低系統功耗。 -
The first part of the paper is designing the testing project for grounding resistance and insulation resistance in a new way. using 16bits ad converter with programmable control amplifier replaced the way which used changing resistance to change measure range. lt is not only improved testing precision and develop the system expediently, but also reduced the area of the circuit boardwith the new way. in order to make the electric implement safety testing system have upstanding expansibility, the software and hardware of the system adopted the modularization design. adopted mcu atmegal28 as a master mcu which control mmi, realtime clock and communication with slaver mcu. atemga8 as the slaver mcu to realize testing function. so it is easy to add or reduce the testing project. the testing implement system has been developed successfully, and the comments for the system is that it has high precision, high expansibility and easy maintain. but considering the electric implement system should have intelligence and humanity abi lity. so this paper bring forward a scheme of electric equipment safety testing embedded system with speech control. after introduce the basic theory of speech recognition, the paper expatiate the characters of this system. the system is a noise conditon, not special people, small glossary, insulation word system. with these characters design the speech recognition as fellow. utilizing cross zero ratio and short energy to ensure jumping - off point and end point ; adopting mfcc as the character parameters of speech recognition ; the character parameters than be recognized by dtw. in order to ensure the credibility of this project, first realized by matlab in computer
在介紹了語音識別的基本原理后，闡述了本系統的特點：本系統是一個噪聲環境下非特定人、小詞匯量、孤立詞的語音識別系統。根據本系統的這些特點設計了如下語音識別方案：利用過零率和短時能量相結合的方式確定語音端點；採用mel頻率倒譜系數（ mfcc ）作為語音識別的特徵參數；得到的特徵參數最後通過動態時間規整（ dtw ）的模式識別方法進行識別。為了確保本系統實現方案的可靠性，首先通過計算機利用matlab軟體來模擬，在演算法模擬實現后又進一步增加環境的復雜性：加上較大的環境噪聲、突發性的噪聲等，再通過修改參數、修改參考模板、兩級識別等各種提高語音識別精度的方法來提廣東工業大學工學碩士學位論文高識別率。 -
In the beginning, the whole design flow is introduced. in the system design, the arithemetic about the memory structure, the enumeration of transfer mode the realization of the control endpoints., the non - control endpoints, the configuration finit state machine > the configuration rom, the interrupt request the function of resume and remote wake - up, the system clock and the five interfaces are achieved
首先介紹了該外圍控制ip所採用的設計流程，接著闡述了系統級的設計，主要包括內存結構、傳輸模式檢測、控制端點與非控制端點的實現、配置有限狀態機、配置rom 、中斷請求、恢復掛起功能、系統時鐘域與復位以及各種介面電路的設計。 -
First, we introduced the basic operation princinple of a - t - m & c - s and its function modules. subsequently, we divided the system into six major modulars : real - time clock function modular, real - time process schedule modular, distribute db management modular, net - work monitor modular, message control modular, and mistake torlerance modular
按中間件特性，把系統劃分為6個主要的管理控制模塊，分別為實時時鐘管理模塊，實時進程調度管理模塊，分散式數據庫管理模塊，網路監控模塊，消息管理模塊，和系統容錯管理模塊。 -
The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit
硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。 -
The third, according to the aforementioned project, a hardware system is provided which includes the core chip - tms320dsc21 ( ti special dsp ) and its peripheral circuits ( clock and power supply ), video input module, network output module, alarm module, and cradle head control module. the design and debug of hardware system is finished
接著以ti公司的專用dsptms320dsc21為核心，進行了嵌入式網路攝像機的硬體設計，硬體部分包括： dsc21核心及相關電路（時鐘、電源和調試電路） 、視頻輸入模塊、視頻數據網路輸出模塊、報警模塊和雲臺控制模塊。 -
We have set up the first tap water surveillance center in taiwan to take control of the operation of the water supply system around the clock
本處成立全國第一座自來水監控中心，二十四小時全年無休，隨時掌握供水系統的運作狀況。 -
The air traffic control complex ( atcx ), located at the centre of the airfield, is the nerve centre of the entire air traffic control system. some 330 air traffic controllers and supporting staff work around - the - clock to provide air traffic control services for the safe and efficient flow of aircraft movements within the hong kong flight information region ( fir )
位於機場中心位置的航空交通管制大樓（航管大樓）裝置了航空交通管制系統的核心設備。航管大樓內有約330名航空交通管制員及支援人員，提供24小時的航空交通管制服務，確保在香港飛行情報區內的航空交通既安全又具效率。 -
The product are widely used for wireless communication, mobile telephone, home electrical appliances, clock, pager, digital camera, remote control system, computer domain, line control system, digital electronic instrument, military equipment, spaceflight industry, tec
產品廣泛應用於無線通訊、移動電話、家電、鐘表、尋呼機、數碼相機、遙控系統、計算機領域、線路控制系統、數碼式電子儀器，軍事設備，航天工業等高科技領域。 -
Based on the introduction of the systematic structure and working principle of pet, the thesis mainly described the realization of the partial function in the mechanical and electrical control system. furthermore, the thesis referred the design of a new circuit of fan - out of high frequency clock
本文在介紹正電子發射斷層掃描儀系統結構及工作原理的基礎上，著重對該儀器機電控制系統的部分功能實現作了詳盡描述，並且介紹了一種新型的高頻時鐘扇出電路的設計。 -
Analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm. the system use input clock as system clock and use parallel structure in system to provide flexible speed
採用適合fpga特點的溢出控制設計方法;改進傳統的寄存器交換法re （ registerexchange ）的倖存路徑管理設計方法;全系統採用輸入數據的同步時鐘作為系統時鐘，系統內部採用全并行的方式，以提供靈活的速度。
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