clock flip-flop 中文意思是什麼

clock flip-flop 解釋
時鐘觸發器
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • flip : vi （ pp ）1 用指頭彈；輕輕打。2 （用鞭子等）抽。3 叭嗒叭嗒地動；翻動紙張。4 跳上車。5 起強烈反應...
  • flop : vi （ pp ）1 鼓翼；撲拍，跳動。2 啪嗒躺下[放下、坐下]；〈美俚〉上床。3 突然轉變。4 徹底失敗。vt ...
  1. Furthermore, low power flip - flop design by reducing the short - circuit power which relates with clock overlapping is also mentioned in this paper

    此外，由於觸發器的短路功耗和控制觸發器的時鐘信號的交迭程度有關，因此文章還對通過合理規劃時鐘信號的交迭來達到減少觸發器短路功耗的低功耗觸發器結構進行了討論。
  2. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  3. According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design

    為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。
  4. Based on the construction of traditional flip - flop, we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock. then this principle is adopted in ternary circuit, a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed

    在二值單閂鎖結構邊沿觸發器的基礎上，把利用時鐘信號競爭冒險的思想應用於三值電路中，提出了基於cmos傳輸門的二值d型時鐘信號競爭型邊沿觸發器。
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