clock register 中文意思是什麼
clock register
解釋
時鐘寄存器-
To eliminate the bootless power dissipation of the redundant transition of the clock, a design method named det ( double - edge - triggered ) shift register is proposed
摘要從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。 -
Then, we propose a design method named det ( double - edge - triggered ) shift register to eliminate the bootless power dissipation of the redundant transition of the clock
接著，從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。 -
Excepting algorithms self, the software performance analysis and optimization always relate to the multi - hiberarchy storage archtechture, trying to utilize the nearside storage media such as register or level 1 cache and reduce actions on farside storage, and try to reach a linear performance, i. e. the computing performance only relate to the speed of cpu clock
現在的軟體性能分析及其相關的性能優化，除了程序本身演算法之外，幾乎所有的分析和優化都是在這樣一個多級的存儲體系結構上進行的，試圖盡可能地利用近端的存儲，期望達到一個接近線速的計算性能，即計算的性能僅由cpu的處理速度決定，與其他外設和數據存儲無關。 -
Versions register less than the clock granularity
兩個版本的注冊時間都小於時鐘間隔大小。 -
For instance the equity day that register is today, so when ending to received city at 3 o ' clock this afternoon, always the partner of this company stock has hold rights and interests, computer is self - recording
比如股權登記日是今天，那麼截止到今天下午3點收市的時候，凡是持有這個公司股票的股東都有權益，電腦自動記錄。 -
Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method
該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號，用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率，而且這一調頻過程幾乎是連續的（實際上是眾多離散點構成的線性近似） 。 -
Error : vhdl error at shift. vhd ( 18 ) : can ' t infer register for signal " q [ 3 ] " because signal does not hold its value outside clock edge
每個時鐘上升沿移位一次，按您說的要加循環吧.移位一次沒問題，加上循環就不行了，有錯誤 -
The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition
表2中第三行表示計數器的同步平行的加載，和表明如果s1和s0為高電平，那麼它就不是連續輸入，在時鐘由低向高跳變后，在a端的數據輸入則在qa端輸出，在b端的數據輸入將在qb端輸出，等等。 -
If it is possible for that register to be linked to a dealing system for that financial product and a payment system to effect money settlement, then, theoretically, dealing, payment and delivery could all be synchronised and done real time, around the clock
若能將某項金融產品的電腦化記錄跟交易系統和支付系統的網路接通，那麼理論上該產品的買賣支付及交收便可即時同步進行，而且全日 -
Calculation for the data from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register
對模擬所得數據的計算結果表明，與實現相同功能的單邊沿移位寄存器相比，由於工作頻率減半，雙邊沿移位寄存器的功耗有明顯降低。 -
Calculation for the data resulted from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register
對模擬所得數據的計算結果表明，與實現相同功能的單邊沿移位寄存器相比，由於工作頻率減半，雙邊沿移位寄存器的功耗有明顯降低。 -
Analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm. the system use input clock as system clock and use parallel structure in system to provide flexible speed
採用適合fpga特點的溢出控制設計方法;改進傳統的寄存器交換法re （ registerexchange ）的倖存路徑管理設計方法;全系統採用輸入數據的同步時鐘作為系統時鐘，系統內部採用全并行的方式，以提供靈活的速度。
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