clock signal 中文意思是什麼

clock signal 解釋
時鐘信號
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • signal : n 1 信號，暗號；信號器。2 動機，導火線 （for）。3 預兆，徵象。adj 1 暗號的，作信號用的。2 顯著的...
  1. The tft lcm driver signals were enable signal and fiducial clock signal, which were strict with synchronization

    驅動信號主要為使能信號和基準時鐘信號，並要求二者具有嚴格的同步性。
  2. A clock signal with 1 million pulses per second is referred to as a 1 megahertz.

    每秒鐘有一百萬個脈沖及時鐘信號，也稱兆赫（）時鐘信號。
  3. A clock signal with 1 million pulses per second is referred to as a 1 megahertz

    每秒鐘有一百萬個脈沖及時鐘信號，也稱兆赫（ ? ）時鐘信號。
  4. The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.

    你的微型計算機執行程序的速度將與你的時鐘信號的速度成線性關系。
  5. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  6. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  7. The main research contents of this dissertation are shown in the following : ( 1 ) introduce one method of use the counting pulse to develop ie measuring system and new method of using the high frequency clock signal to divide the space pulse

    本文主要研究內容如下: （ 1 ）系統論述了一個脈沖計數方式的ie測量系統的測量原理，闡述了一個採用高頻的時鐘信號細分空間脈沖的新型細分方法。
  8. The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5

    電平調節電路100將送往第一個時鐘終端ck1的時鐘信號從h電平降低一個預定值，並將此信號送往晶體管q5的輸入端。
  9. Oscillator generated a wave with frequency 132 khz as the clock signal

    振蕩器電路產生一個頻率在132khz附近抖動的矩形波作為整個電路的時鐘信號。
  10. The transition from voltage to no voltage is referred to as the trailing edge of a clock signal.

    電感從一定值下降到0值的躍遷叫做時鐘信號的后沿。
  11. The device always generates the clock signal

    時鐘信號總是由設備端生成的。
  12. Real - time power angle measurement of a synchronous generator based on gps clock signal and tachometer

    時鐘信號的發電機功角實時測量方法
  13. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  14. The following is main content of our thesis. the first, we analyze the system operation theory of cmos image sensor with pixel level adc ( a / d converter ). it is made up of three sections : pixel array, clock signal generator and sam ( sequential access memory )

    本文的主要內容如下：首先，我們對像素級a d轉換型圖像傳感器的系統工作原理進行了分析，是由像素陣列、時鐘信號產生器和sam （順序讀寫存儲器）三部分構成的。
  15. The principle of the method is to introduce a clock isolation circuit which tracks clock transitions just like a clock signal, yet isolates the clock from the “ clock - used - as - data ” logic

    主要的方式是導入時鐘隔離電路追蹤時鐘轉換如時鐘訊號，然後"時鐘做為資料"邏輯做為隔離時鐘技術。
  16. This paper gives a time - synchronization technique bases on gps time service signal which is used in broad band seismic recorder 。 by world coordination time offered by gps - - utc ( usno ), adjust local clock base on gps signal, gain high nicety clock signal, clock precision reachs 10 - 6 。 this clock is the time source of broad band seismic recorder, bring the whole seismic recorder works in same time base. 1pps time base with high stability can be used as in - phase, spring, time and start - stop of every collection mode, while the scale under second make a precise time mark to receive data of broad band seismic recorder

    針對接收機中gps信號的噪聲進行kalman濾波軟體處理， kalman濾波可以對gps信號與本地晶振時鐘的時差數據在大噪聲中進行平滑，在較短時間內估計出高精度的時差數據。系統消除了gps秒脈沖信號的ms級隨機誤差，把晶振秒脈沖的長期穩定度鎖定到gps信號的穩定度上;在gps信號失效時給出了可行措施，能夠保證在任何情況下產生一個穩定、高精度秒脈沖信號，誤差在1 s內。
  17. An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications

    提出了一種改進的高精度電流型排序電路.它的結構復雜性僅為o （ n ） ，便於擴展;動態范圍大;它是自適應的，工作點由輸入電流確定，故不需要偏置信號，這對作為通用器件使用的排序電路來說是很重要的.通過利用平均值電路、減法電路、 wta電路和控制電路，可以使該電路在大輸入電流下依然保持高性能. hspice模擬表明該電路具有高準確性、高精度、低功耗的特點.它能用標準數字cmos工藝來實現，可以被應用於很多領域，具有很高的應用價值
  18. Again, the keyboard / mouse always generates the clock signal, but the host always has ultimate control over communication

    重復一遍，鍵盤/鼠標總是生成時鐘信號，而主機控制著整個通信過程。
  19. All signals, except for the clock signal, are limited in one block or between two adjacent blocks

    除了全局時鐘之外的信號都被限定在一個模塊內部或者相鄰的2個模塊之間。
  20. Aiming at the scheme of the signal electromagnetic environment simulator of the wireless communication system, the mission of this project is to design and realize twenty - four frequency synthesizers, which must meet high expectation for the phase noise characteristic and the spurious repression characteristic of the output clock signal. these frequency synthesizers provide the moving of the basic signal generating modules to radio frequency with stable inspiring source

    本課題的任務是針對通信信號電磁環境模擬器系統的方案要求，設計實現24個（頻率分佈在260mhz 1430mhz之間）對輸出時鐘信號的相位噪聲特性、雜散抑制特性等要求都很高的頻率合成器，為基本信號生成模塊到射頻的搬移提供穩定可靠的激勵源。
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