combinational circuit 中文意思是什麼

combinational circuit 解釋
組合電路
  • combinational : 組合的
  • circuit : n 1 (某一范圍的)周邊一圈;巡迴,周遊;巡迴路線[區域];迂路。2 巡迴審判(區);巡迴律師會。3 【...
  1. Design basis of combinational logic circuit

    組合邏輯電路設計基礎
  2. In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld

    本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。
  3. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory. in 1995, barenco showed that almost any two - bit gate is universal, so building a feasible two - bit logic gate is the first step to engineer a quantum computer. in principle, the quantum bit can be carried by any two states system

    在眾多的量子計算機模型中目前討論最廣泛的是量子計算機門組網路模型,量子計算機門組網路模型是經典計算機門組網路結構的量子推廣,它是根基於barenco等人所證明的「一個兩比特受控操作和對單比特進行任意操作的門可以構成一個『通用量子邏輯門組』 」之上的。
  4. In this paper 5 function modek equivalent circuit model and p matrix representation of idt are expounded. the principle of energy transfer efficiency of energy transfer and frequency response of combinational acoustic pathes are also expounded

    本論文闡述了叉指換能器的6函數模型、等效電路模型和p矩陣表示方法;耦合器能量轉移的原理、能量轉移效率;組合聲路的頻率響應。
  5. The method of optimization is classified into two categories : ( 1 ) combinational optimization method, which is the optimizational method of combinational circuit is directly used for the sequence circuit

    優化的方法大致可分為兩類: ( 1 )組合優化方法,即將組合電路的優化方法直接用於時序電路。
  6. Delay analysis of combinational circuit in using programmable logic device

    用可編程邏輯器件進行組合電路設計時的延時分析
  7. During test, some registers in the processor are converted into scan chains to improve controllability of the circuit, the adders in the processor are used as test generators, and the produced test patterns can detect any combinational faults within every basic building cell of fft processor

    測試時,該方案將處理器中的寄存器作為掃描鏈提高了其可控性,利用其中的加法器作為測試生成,生成的測試矢量能偵測處理器每個基本組成單元內部的任意組合失效。
  8. Combinational logic circuit

    組合邏輯電路
  9. A combinational circuit with only one output channel

    一種只具有一個輸出通道的組合電路。
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