decoder circuit 中文意思是什麼

decoder circuit 解釋
解碼器電路
  • decoder : n. 譯電員；譯碼機；解碼器；判讀器。
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  1. Bcd detail specification for electronic component. semiconductor integrated circuit. type ch2019 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路ch2019型4線- 10線譯碼器
  2. The paper is to design analogue lowpass filtering circuits with high performances. the circuits are used directly as anti - alias filters in an analogue front - end of video decoder ic ( integrated circuit )

    =本文旨在設計高性能的模擬低通濾波電路，用作視頻解碼晶元模擬前端中的抗混疊濾波器。
  3. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  4. The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier

    Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。
  5. Detail specification for electronic component. semiconductor integrated circuit - type cd 7343 gs phaselocked loop fm stereo decoder

    電子元器件詳細規范.半導體集成電路cd 7343 gs型鎖相環調頻立體聲解碼器
  6. Based on the realization of the encoder / decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation. the fprme decoder is advanced in the world. the parallel fec circuit completely conforms to the itu - t protocols, and has important practical value

    在rs （ 255 ， 239 ）硬體編碼器/解碼器實現的基礎上，本文按照gpon協議要求，針對gpon中最高速率2 . 488gbps的下行幀，通過設計復雜的操作時序，實現了符合協議規定的32位并行fec編解碼和解擾碼電路，並作了模擬。
  7. This is the core of the issue. in this section we designed the cells of the dac, including the decoder circuit, bandgap reference voltage circuit, current source circuit and switched circuit etc. the fourth chapter the simulations of circuit and errors of the dac are discussedi, so the simulation waveforms are plotted on the paper and we must take the error corrections and minimize ways

    對于整個d a轉換器的具體結構和電路設計放在第三章，這也是本文的核心之處，對d a轉換器的整體電路及主要電路單元如：數字譯碼電路、帶隙參考電壓源電路、電流源產生電路、差分電流開關電路等進行詳細地分析和設計。
  8. The results of the hdl simulation and fpga verification showed that image enhancement improved greatly the image quality. cooperating with software a circuit that can read and write flash memory and a remote controller hardware decoder were also designed in this thesis. after hdl

    本文還設計了與軟體配合能讀、寫閃存的電路以及紅外遙控的硬體解碼電路，經hdl模擬及fpga驗證，所設計的兩種電路能完全滿足晶元商用要求。
  9. This paper describes the error control coding of the flex paging system, with emphasis on the design and implement of the flex decoder circuit by means of the fpga technology

    本文介紹了flex高速無線尋呼系統中的差錯控制編碼技術，以及bch （ 32 ， 21 ）糾錯碼的構成和譯碼方法，重點討論了flex高速尋呼解碼晶元的fpga設計與實現。
  10. This paper is to discover the clamp circuits for realizing video decoder ic ( integrated circuit ), and focusing on realizing the function of video clamp circuit and project design with cmos process

    本文旨在探索為實現視頻解碼晶元的模擬前端而作的箝位電路設計。重點論述了在cmos工藝下視頻箝位電路的功能實現及設計方案。
  11. The application of hardware decoding circuit is widely, because it not only can be used on computer, but also can be used on consumer equipment like digital - tv and dvd - player. the avs and h. 264 standards and the architecture of digital video decoder chip are investigated in the thesis, and a high - definition multi - mode decoder soc chip is proposed. the chip can support avs level 4. 0 / 6. 0 and h. 264 main profile level 4. 0

    本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼晶元系統結構的基礎上，設計了同時支持avs和h . 264的高清解碼soc晶元，能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。
  12. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
  13. Detail specification for electronic components. semiconductor integrated circuit ct54ls138 ct74ls138 3 - to - 8 line decoder

    電子元器件詳細規范.半導體集成電路ct54ls138 ct74ls138型3線? 8線譯碼器
  14. Bcd detail specification for electronic component. semiconductor integrated circuit - cc4028 cmos 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路cc4028型cmos 4線? 10線譯碼器
  15. Detail specification for electronic components. semiconductor integrated circuit ct5442 ct7442 4 - line - to - 10 - line decoder bcd - to - decimal

    電子元器件詳細規范.半導體集成電路ct5442 ct7442型4線- 10線譯碼器bcd輸入
  16. The two methods, an all - parallel viterbi decoder and an optimized viterbi decoder are represented. the former one is small constrained, simple construction and large resource consuming while the latter one is long constrained, complicated construction and small resource consuming. employing the digital circuit optimize algorithm, the latter one has already covered design thoughts of present viterbi decoder

    對于viterbi譯碼器，描述了適用於小約束度、結構簡單、資源耗費較大的全并行viterbi譯碼器和使用於大約束度、結構復雜、資源耗費較小的優化viterbi譯碼器，其中，優化viterbi譯碼器採用viterbi譯碼優化演算法和數字電路設計的優化演算法，基本已涵蓋了當前viterbi譯碼器的設計思路。
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