design and development verification 中文意思是什麼

design and development verification 解釋
設計開發驗證
  • design : vt 1 計劃，企圖，立意要…。2 指定，預定；留給，留著。3 設計，草擬，擬定，籌劃；起草，畫草圖，打（...
  • and : n. 1. 附加條件。2. 〈常 pl. 〉附加細節。
  • development : n. 1. 發展，發達；進化。2. 展開；擴充；開發。3. 發達物，新事物，發展階段。4. 【生物學】發育（史）；【軍，數】展開；【攝影】顯影，顯像；【音樂】展開（部）；研製，研製成果。
  • verification : n. 1. 證實，證明，確定；核驗，驗證，核對；檢驗，校驗。2. 【法律】訴狀[答辯書]結尾的舉證說明。
  1. Developing the lithography process models to properly characterize critical dimension ( cd ) variations caused by proximity effects and distortions introduced by patterning tool, reticule, resist exposure, development and etching, they are beneficial to develop a yield - driven layout design tool, the engineers could use it to automate the tasks of advanced mask design, verification and inspection in deep sub - micron semiconductor manufacturing

    建立準確描述由於掩模製造工藝、光刻膠曝光、顯影、蝕刻所引起的光學鄰近效應和畸變所導致的關鍵尺寸變化的光刻工藝模型，有助於開發由成品率驅動的版圖設計工具，自動地實現深亞微米下半導體製造中先進的掩模設計、驗證和檢查等任務。
  2. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  3. With the rapid development of the semiconductor process and relevant technology, beyond the traditional integrated circuit, system - on - a - chip ( soc ) is coming up. it consists of a lot of intellectual property ( ip ) blocks and embedded processors, which require a piece of embedded software code to be composed. with design complexity beyond the traditional chips, verification difficulty is growing up

    系統晶元是隨著集成電路的發展而出現的新一代晶元，在系統晶元的設計中大量採用ip核復用技術，系統晶元中還包含有嵌入式的處理器，因而需要同時設計嵌入式的軟體程序，其設計復雜度遠遠高於傳統的ic晶元。
  4. In the electronic industry today, the combination of increasing complexity of todays asic and systems designs and relentless time - to - market ( ttm ) pressures has resulted in verification, especially functional verification, jumping to the top of the list of bottlenecks in the design and development of electronic products utilizing soc

    近幾年來隨著專用集成電路（ asic ）和系統晶元（ soc ）的復雜度的不斷提高，以及來自面市時間的巨大壓力，晶元驗證，尤其是功能驗證正日益成為電子產品開發和設計的「瓶頸」 。
  5. This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design

    本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。
  6. To provide technology support for outsourcing processing and purchasing during product development period, to establish production & processing technical agreement and purchasing technical agreement, to participate in product design verification, also responsible for establishing plan specifications, test procedures and engineering bom, and completing design records needed for the quality system

    對產品開發階段的外協加工製造和采購提供技術支持，制定製造加工的技術協議和采購技術協議，參與產品設計驗證過程並負責設計的規格書編制，檢驗規程和工程bom編制，按規定完成質量體系要求的設計記錄。
  7. Design and implementation of a fast round robin scheduler, in which a pipelined barrel shifter and a pipelined priority encoder are used ; testbench development of functional simulation for module verification and system verification, in which the bfm simulation model are used and some reference examples are proposed ; discussing the questions that should be paid attention to when using fpga to design high speed circuits and some design skills ; taking part in the system ' s integration and fpga implementation ; taking part in the system ' s test and verification ; the design of this thesis has provided some key method for inter - communication among different network processors, and also accelerated the development of communication products

    討論了用fpga設計高速電路應注意的問題和一些常用的設計技巧；參與整個轉換邏輯的系統集成和fpga實現；參與系統的驗證工作；通信協議轉換邏輯的設計不僅可以解決不同網路處理器之間互通的問題，而且對于促進國產數據通信產品的研究與開發具有很重要的意義。同時在設計的過程中，進一步地探討了基於fpga的高速電路設計技術，對于fpga的設計有參考價值。
  8. To solve the problems in code design of information system development such as deviate standard, unreasonable structure, and incomplete contents, this paper puts forward concrete processing suggestion as follows : code design must ( 1 ) strictly conform to the national standard ( gb series ) ; ( 2 ) not only fully consider its extendibility and reasonability, but also its simplification and stability ; ( 3 ) have code verification for any codes used in the information system development

    針對信息系統開發中代碼設計存在的不符合標準、結構不合理、內容不完全等問題，提出了嚴格按國家標準設計、處理好代碼的可擴充性與簡明性原則的統一，代碼結構的合理性與穩定原則的統一、設計內容必須包括代碼校驗等具體的處理意見。
  9. The outputs of design and development shall be provided in a form that enables verification against the design and development input and shall be approved prior to release

    設計與開發輸出的格式必須能和設計與開發輸入相驗證，且在發出前被核準。
  10. Verification shall be performed in accordance with planned arrangements ( see 7. 3. 1 ) to ensure that the design and development outputs have met the design and development input requirements

    為確保設計和開發輸出滿足輸入的要求，應對依據所策劃的安排（見7 . 3 . 1 ）設計和開發進行驗證。
  11. Is a software verification tool set that overcomes complexities of the embedded software environment from early - phase host - based design and development to final - phase test and validation

    是軟體校驗工具組，克服從最初基於主機的設計及開發階段到最終測試及校驗階段的嵌入式軟體環境的復雜性，有助於節省時間和資金。
  12. With the development of ic manufacture process and the enhancement of its design complexity, the verification requirement to ic is much higher

    隨著集成電路製造工藝的發展和設計復雜度的增長，對集成電路的驗證提出了更高的要求。
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