divider stage 中文意思是什麼

divider stage 解釋
分頻級
  • divider : n. 1. 劃分者；分割者；分裂者，離間者。2. 間隔物；分裂的原因。3. （割禾機等的）分切器；【數學】除數；除法器；【電學】分壓器；【航空】減速器。4. 〈 pl. 〉劃規，兩腳規，分線規。
  • stage : n 1 講臺；舞臺；戲院，劇場；〈the stage〉戲劇，戲劇藝術；戲劇文學；〈the stage〉戲劇業；劇壇。2 ...
  1. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  2. Binary divider stage

    二進制分頻級
分享友人
分享到 Line

分享到臉書