drain current 中文意思是什麼
drain current
解釋
漏電流-
Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet
基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高 -
In gan hemt drain pulse current collapse experiments, drain current under pulse condition collapsed about 50 % than direct current condition and the pulse signal frequency affected little on current collapse. when gate voltage is small, the relationship between pulse width and drain current is i0 ( + t / 16 )
在ganhemt漏極脈沖電流崩塌測試中，發現脈沖條件下漏極電流比直流時減小大約50 % ;脈沖信號頻率對電流崩塌效應影響較小;當柵壓較小時，隨著脈沖寬度的改變漏極電流按i0 （ + t / 16 ）的規律變化。 -
Under pulse condition, charging and discharging of surface states between gate and drain induce gan hemt current collapse
脈沖條件下， ganhemt電流崩塌效應主要由柵漏之間表面態充放電引起。 -
In this paper, the theory of negatively charged surface states is used to investigate dynamic breakdown characteristics and the increase of gate - drain breakdown voltage as well as the reduction of saturated drain - source current after sulfur passivation. the measure which can improve the stability of sulfur passivation is proposed
本論文通過對gaasmesfet擊穿機理和硫鈍化機理的研究，用負電荷表面態理論，解釋了gaasmesfet動態擊穿特性及硫鈍化后柵漏擊穿電壓增大、源漏飽和電流減小的機理，提出了改善硫鈍化穩定性的措施。 -
In gan hemt gate pulse experiments, drain current under pulse conditon collapsed about 47 % than direct current condition and the pulse width affected little on current collapse. the relationship between drain current and pulse frequency is ncoxw [ m + ( n + k ? ) vgs + ( n + k ? ) vgs2 ] ( vgs - vth ) 2 / l
在ganhemt柵極脈沖電流崩塌測試中，觀察到柵脈沖條件下漏極電流比直流情況下減小了47 % ;隨著信號頻率的改變，漏極電流按ncoxw [ m + （ n + k -
Based on the hydrodynamics energy transport model, the degradation induced by donor interface state is analyzed for deep - sub - micron grooved - gate and conventional planar pmosfet with different channel doping density. the simulation results indicate that the degradation induced by the same interface state density in grooved - gate pmosfet is larger than that in planar pmosfet, and for both devices of different structure, the impact of n type accepted interface state on device performance is far larger than that of p type. it also manifests that the degradation is different for the device with different channel doping density. the shift of drain current induced by same interface states density increases with the increase of channel do - ping density
基於流體動力學能量輸運模型，對溝道雜質濃度不同的深亞微米槽柵和平面pmosfet中施主型界面態引起的器件特性的退化進行了研究.研究結果表明同樣濃度的界面態密度在槽柵器件中引起的器件特性的漂移遠大於平面器件，且電子施主界面態密度對器件特性的影響遠大於空穴界面態.特別是溝道雜質濃度不同，界面態引起的器件特性的退化不同.溝道摻雜濃度提高，同樣的界面態密度造成的漏極特性漂移增大 -
In order to do the research works above better, we must can precisely control the width of the quasi - 1d channel and the cut off point, and also must precisely inspire current in the 2deg, so we designed the 2 channel high precision and high stability voltage source, one channel can supply the minus voltage to the split - gate, and the other one can supply the offset voltage between the source and drain pole
為了進行上述研究，必須能夠精確的控制準一維電子通道的寬度和鉗斷，以及精確的在2deg上激勵電流，由此我們設計研發了給分裂門加負偏壓和給準一維電子通道加源漏偏壓的兩路高精度高穩定性饋源。 -
The emphases of our research works are as follows : under ultra - low temperature ( about 0. 236k ) conditions, how the frequency and power of the saw and the source drain voltage influence the acoustic current ; and the relationship between the source drain current and the split - gate voltage ; and how to find the cut off voltage of the quasi - 1d electron channel ; and also the frequency character of the idt in the saw parts
研究的重點為，在甚低溫（ 0 . 236k ）下，通過實驗研究表面聲波的頻率和功率，源漏偏壓等因素對聲電電流的影響;研究準一維電子通道中不同源漏電流與分裂門負偏壓的關系，以找到分裂門的鉗斷點電壓;以及研究聲表面器件叉指換能器的頻率特性等。 -
In this paper, the working principle of the interleaving two - transistor forward converter is analyzed in detail, and the waveforms of the switch drain - to - source voltage and transformer magnetizing current are researched in different duty cycle conditions. the simulation model is constructed and the simulation results verify the analysis
本文分析了交錯並聯雙管正激變換器的工作原理，研究了在不同占空比條件下開關管的漏源電壓和變壓器勵磁電流波形，建立了模擬模型，模擬結果證明理論分析的正確性。 -
As a result, the fermi level at the surface will shift towards the valence band maximum ( vbm ). accordingly the band bending increases, and the surface depletion layer thickness enhances, therefore, the channel thickness reduces. this is the main factor resulting in the decrease of saturated drain - source current
表面費米能級向價帶頂移動，能帶彎曲加劇，肖特基勢壘高度增加，表面耗盡層變厚，導電溝道變窄，是導致源漏飽和電流下降的主要因素。 -
Small signal jfets work very well as low - leakage diodes by connecting drain & source together in log current - to - voltage converters and low leakage input protection
在對數電流-電壓轉換器和低漏電流輸入保護電路中，通過連接小信號jfets的漏極和源極，可以使之作為低漏電流二極體很好的使用。 -
Under high drain voltage condition, the results proved that channel electrons are easily ejected into gan buffer layer and be trapped to induce current collapse
在大漏極電壓條件下，溝道電子易於注入到gan緩沖層中，並被緩沖層中的陷阱所俘獲，耗盡二維電子氣，從而導致電流崩塌效應。 -
Under a unified model of carrier transport over trap state established potential barrier at drain side, device degradation behavior such as asymmetric on - current recovery and threshold voltage degradation can be understood
我們通過載流子在漏極附加陷阱態勢壘的輸運模型，解釋了器件在應力后出現的閾值電壓的退化現象和非對稱性開態電流恢復現象。 -
We discussed the influence of channel - length modulation effect and dibl effect to temperature behavior of source - drain current, gave a expressions for studying the temperature characteristic of source - drain current, and deduced a ztc point expression
研究了溝長調制效應和漏致勢壘降低效應對漏源電流溫度特性的影響，給出了一個用於研究漏源電流溫度特性的電流公式；並推導了短溝道most的ztc點公式。 -
After structure design aimed to high transconductance, parameters of device structure are modified in detail. the simulation results of soi nmos with strained si channel show great enhancements in drain current, effective mobility ( 74 % ) and transconductance ( 50 % ) beyond conventional bulk si soi nmosfet. the strained - soi nmosfet fabrication process is proposed with lt - si ( low temperature - si ) technology for relaxed sige layer and simox technology for buried oxide
其次，根據器件參量對閾值電壓和輸出特性的影響，以提高器件的跨導和電流驅動能力為目的設計了strained - soimosfet器件結構，詳細分析柵極類型和柵氧化層厚度、應變硅層厚度、 ge組分、埋氧層深度和厚度以及摻雜濃度的取值，對器件進行優化設計。 -
Physics device model, component structure design and fabrication technology are discussed based on the thorough analysis of strained silicon and soi physics mechanism. the detail contents are as follows. the analytical threshold voltage model, drain current model and transconductance model are derived from poisson ’ s equation for the fully depleted strained soi mosfet
本論文圍繞這一微電子領域發展的前沿課題，在深入分析應變硅和soi物理機理的基礎上，對器件的物理模型、器件結構設計和工藝實驗等問題作了研究，主要包括以下幾部分:首先，從器件的物理機制出發，建立主要針對薄膜全耗盡型器件的閾值電壓、輸出電流和跨導模型。 -
The effect of interface state charges on the threshold voltage, drain current, transconductance and field - effect mobility of n - channel sic mosfet is analyzed with numerical method by establishing the model of the interface state density exponential distribution
建立界面態密度的指數分佈模型，用數值方法較為詳細的分析了界面態電荷對n溝mosfet器件閾值，漏電流，跨導和場效應遷移率的影響。 -
Considering the unsymmetrical distribution of interface states induced by hot - carrier effects along the channel, the quasi - two - dimensional analysis methods are used to deduced the drain current, threshold voltage and electrical field in channel after hot - carrier degradation and the theoretical results are fully verified with the experimental data and m1ntmos6. 0 simulation output. the degradations of device output conductance, subthreshold conduction and rf characteristics are also analyzed
針對mos器件熱載流子退化所引入的界面態，根據其沿溝道非均勻分佈的模型，採用準二維分析方法對退化后器件的漏源電流、閾值電壓和飽和區溝道電場作了詳細的理論推導，並與實驗結果和器件二維數值模擬軟體minimos6 . 0的計算結果進行了驗證比較。 -
We probed into the most source - drain resistance and its temperature behavior particularly. the result of calculation indicated that the attenuation of source - drain current caused by the source - drain resistance increased when temperature increased
對寄生的漏源串聯電阻及其溫度特性進行了詳細探討，計算結果表明，漏源串聯電阻給漏源電流造成的衰減在溫度升高后變得很大。 -
The study shows that interface state charges not only increase the threshold voltage, but also lower the mosfet transconductance, drain current and field - effect mobility, which can well explain the results of experiment
分析結果顯示界面態電荷不僅使閾值電壓增大，而且還會導致器件漏電流減小，跨導和場效應遷移率降低，模擬結果能對實驗現象做出很好的解釋。
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