extraction parasitic 中文意思是什麼

extraction parasitic 解釋
寄生析出
  • extraction : n. 1. 抽出，拔出。2. 【化學】提取（法）；萃取（法）；回收物，提出物；精煉。3. 精選，摘要。4. 血統，家世，出身。5. 【數學】開方，求根。
  • parasitic : adj. 1. 寄生的，寄生動[植]物的；寄生體的，寄生質的；（疾病）由寄生蟲引起的。2. 寄食的；奉承的。adv. -cally
  1. The mixed - signal flow should realize the communication between the digital circuit and analog one. it includes mixed - signal simulation, integration of the layout of digital and analog circuit, parasitic extraction and post - simulation

    數模混合的設計流程要實現數模電路之間的信號通訊，它的主要流程包括：數字模擬電路的混合模擬，數字模擬電路版圖的整合和數字模擬電路提取寄生參數后的模擬。
  2. These rules are based on the extraction of all parasitic parameters of the layout and device modeling, including transition behavior, high frequency characteristics of the different materials, and electrostatic couplings to printed circuit board ( pcb ) conductors and to the ground

    這些規則是基於抽取pcb的敷線和器件模型的所有寄生參數而建立的，寄生參數的抽取考慮到了瞬態行為，不同材料的高頻特性， pcb不同導體和各導體對地間的靜電耦合。
  3. The macromodel is built up with the combination of device simulation and nonlinear curve fit, which makes the extraction of the substrate parasitic parameters more convenient and the circuit simulation more accurate

    該宏模型通過器件模擬與非線性擬合相結合的方法建立，使襯底寄生參數的提取更加方便，同時保障了深亞微米電路特性的模擬精度。
  4. With the software cadence, model establishment and parasitic parameter extraction are made on the main pcb lines of the proposed circuits. equivalent circuit models of common mode combined with differential mode current and noise simulation models are also established on full bridge switching - mode converters. study on the simulation of conducted interference noise is made with the software saber and the effects on the circuits " noise by the main parasitic parameters are also analyzed

    在對全橋開關型變換器電路工作原理分析的基礎上，建立了全橋開關型變換器主要元器件的電磁干擾參數模型，利用cadence軟體對其pcb主要印製導線進行了建模分析和寄生參數的提取，得到了全橋開關型變換器傳導干擾的共模、差模噪聲電流等效電路模型以及噪聲模擬模型，並運用saber軟體進行了傳導性干擾噪聲的模擬研究，分析了主要寄生參數對電路噪聲的影響。
  5. Design flow of analog circuit begins with drawing schematic and includes simulation, layout, drc / lvs check, parasitic extraction and post - simulation

    模擬電路從schematic開始，其設計流程包括：模擬，版圖繪制， drc lvs檢查，寄生參數提取和后模擬。
  6. The traditional methods of parasitic parameter extraction in eda, which based on the concept of lumped component, have lost their accuracy

    傳統的eda設計中的基於集總電路概念的參數提取演算法已經失去準確性。
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