flip flop 中文意思是什麼

flip flop 解釋
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  • flip : vi （ pp ）1 用指頭彈；輕輕打。2 （用鞭子等）抽。3 叭嗒叭嗒地動；翻動紙張。4 跳上車。5 起強烈反應...
  • flop : vi （ pp ）1 鼓翼；撲拍，跳動。2 啪嗒躺下[放下、坐下]；〈美俚〉上床。3 突然轉變。4 徹底失敗。vt ...
  1. Was this another flip - flop from a man who has developed a reputation for confusing financial markets by sounding alternately hawkish and dovish

    難道這是一個已經建立名聲的人再一次變換立場，為的是通過鷹派（激進）和鴿派（保守）兩種作風相交替來干預金融市場？
  2. The most commonly used trigger flip-flop is the master-slave type with cross feedback.

    最常用的觸發器是交叉反饋的主從觸發器。
  3. Information should not be transferred from the master portion of the flip-flop to the slave portion.

    信號不能從主觸發器傳到從觸發器。
  4. Just she and i. we had a great time. i took her to the restaurant in here southern california that is known for its delicious fish tacos, and the price is right for my budget. we made sure we wore a pair of flip - flop sandals and t - shirts, otherwise we would have been very overdressed

    我帶她到南加州最好的餐廳，他們的食物是全球最好的，魚肉玉米片，世界上再沒有更好吃更優惠的魚肉玉米片去這地方，記得要穿人字拖鞋和汗衫，否則就會穿得太隆重了。
  5. As an experiment of basic course in electronic technology, the project is based on domination principle of digital music player and integrates with the elementary application of multiplexer, flip - flop, counter and rom, which enables students to comprehend these knowledge fully along with acquaintance of technical application and promotes systematic understanding of basic notions, course content and advances the transformation from knowledge to ability

    作為數字電子技術基礎課程的實驗內容，該方案設計以數字音樂播放的控制原理為切入點，結合了數據選擇器、觸發器、計數器和只讀存儲器的基本應用，使學生在充分理解這些知識點的同時了解一些工程應用背景，以形成對課程內容、基礎概念的系統認識，促進知識向能力的轉化。
  6. Design of a flip - flop circuit within digital logic analyzer based on fpga

    的邏輯分析儀觸發電路的設計
  7. This clumsy flip - flop has severely undermined the credibility of thailand ' s economic policymakers

    朝令夕改嚴重的打擊了投資者對泰國經濟政策的信心。
  8. Furthermore, low power flip - flop design by reducing the short - circuit power which relates with clock overlapping is also mentioned in this paper

    此外，由於觸發器的短路功耗和控制觸發器的時鐘信號的交迭程度有關，因此文章還對通過合理規劃時鐘信號的交迭來達到減少觸發器短路功耗的低功耗觸發器結構進行了討論。
  9. Flip - flop is the core of sequential circuits, this dissertation designed a synchronous set - reset edge - trigged jk flip - flop based on rt quantum devices, the jk flip - flop has strong function and high speed, and also riches the types of flip - flops in quantum circuits

    所設計的jk觸發器功能強，且與傳統的觸發器相比，基於rt量子器件的邊沿型jk觸發器具有量子器件的功耗低、速度快、電路簡單等特點。本文設計的jk觸發器豐富了量子電路中觸發器的種類，使得量子時序電路的設計更為靈活。
  10. Flip - flop stamp sheetlet to be issued on 30 january to commemorate the opening of the expo

    疊影幻趣郵票小型張將於一月三十日郵博開幕日發行。
  11. While sheetlet no. 1 was issued on 8 april 2003 and sheetlet no. 2 will be issued on 14 october 2003 as a run - up to the expo, tourism series no. 3 to 6 with each depicting a different facet of the expo theme will also be issued consecutively from the first day of the expo. a flip - flop stamp sheetlet will be issued to commemorate the opening of the expo on 30 january 2004

    第一號小型張已於二三年四月八日發行，第二號將于同年十月十四日推出，而以不同的角度展示香港旅遊魅力的第三至六號小型張，則于郵博開幕日起逐日發行。香港郵政亦會於二四年一月三十日郵博首日發行一款疊影幻趣郵票小型張，慶祝郵博開幕。
  12. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  13. In the meantime, the all sub - circuits are also designed and emulated carefully including inverter, rs type flip - flop, voltage reference circuit, error amplifier, voltage comparator, sawtooth - wave generator, pwm comparator, soft activation circuit and so on. as a result, all of the sub - circuits answer the requirements. this chip has taped out with the 0. 5um mix - signal process of csmc

    本文利用cadenceeda集成電路設計工具、 spectres模擬工具，對集成電路內的各個模塊包括反相器、基本rs觸發器、基準電壓電路、誤差放大電路、電壓比較電路、鋸齒波振蕩發生電路、 pwm比較電路、軟啟動電路、驅動電路等進行了具體的設計和模擬，且達到了預先設定的指標。
  14. In meantime, the all sub - circuits are also designed and emulated carefully including error amplifier, voltage reference circuit, voltage comparator, rs type flip - flop, soft - start circuit, sawtooth - wave generator, pwm comparator, current added circuit and so on

    其次對控制器內部晶元的各個模塊誤差放大電器、自舉電流電路、電壓基準源、電流求和電路、 rs觸發器和驅動電路等模塊進行了具體的設計和模擬的邏輯功能做了解釋。
  15. The whole circuit consists of a multiplier, an error amplifier, a comparator, a rs flip - flop, an and gate, and an inverter, etc. the electronic circuit simulator cadence is utilized to practice the detailed functional simulation of the general circuit and the subsystem circuits

    整個電路由模擬乘法器、誤差放大器、比較器、 rs觸發器、與門和倒相器等基本單元電路組成，採用工作站上的大型ic設計軟體cadence進行模擬。
  16. From the concept of triditional master - slave flip - flop, we propose a simplified positive edge - triggered flip - flop and prove the traditional positive edge - triggered flip - flop is the master - slave flip - flop designed based on basic flip - flop with single - rail input

    並且從傳統主從結構觸發器出發，提出了簡化結構的維持阻塞型觸發器設計。針對數字電路中大量存在的冗餘現象，本文討論了冗餘抑制原理以及相應的冗餘抑制技術。
  17. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  18. Semiconductor integrated circuits. detail specification of type je 10531 ecl dual d master - slave flip - flop

    半導體集成電路. je10531型ecl雙d主從觸發器詳細規范
  19. As emphasis, we propose a new backward width - flrst search circuit partitioning method with flip - flop as core for synchronous sequential circuits. and then based on it, we develop a new circuit parallel tg algorithm

    最後重點對電路并行方法進行了研究，提出了一種新的以觸發器為核且消除大功能塊之間反饋的寬度優先反向搜索同步時序電路劃分方法。
  20. Detail specification for electronic component. semiconductor integrated circuit. type ch2005 dual j - k negative - edge triggered flip - flop

    電子元器件詳細規范.半導體集成電路ch2005型雙下降沿j - k觸發器
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