floating bus 中文意思是什麼
floating bus
解釋
浮動總線-
Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design
Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。 -
Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method
在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。 -
There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way
Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。 -
It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc
它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。 -
The work in this thesis was part of a national 05 " project which task was designing the " longtengrl " microprocessor. there are four parts in " longtengrl " microprocessor : integer execution unit ( ieu ), floating point unit ( fpu ), memory subsystem unit ( msu ) and bus interface unit ( biu )
本論文完成存儲子系統單元的設計與實現、 「龍騰r1 」系統的集成、存儲子系統單元的驗證以及在「龍騰r1 」存儲子系統基礎上進行了tracecache的研究，其中重點討論存儲子系統的設計與實現。 -
With zhengzhou railway station, the largest railway hub station in china, the largest passenger bus transport center in henan province, namely, zhengzhou bus passenger transport station, jingguang bus passenger transport station, ermalu bus passenger transport station and railway long distance bus passenger station, this district has unique transport facility, and hosts the largest telecommunication and post hub in the central plains, with a daily average over 2000, 000 floating population, forming increasing stream of people, stream of materials, and stream of information in the central city zone, containing enormous commercial opportunity
區內有全國最大的鐵路樞紐站鄭州火車站，河南最大的汽車客運中心鄭州汽車客運總站，京廣汽車客運總站、二馬路汽車客運站、火車站長途汽車客運站等，交通優勢得天獨厚；中原地區最大的電信、郵政樞紐也位於本轄區，日平均20多萬流動人口，形成了中心地區不斷增大的人流、物流、信息流，蘊藏著巨大的商機。 -
Consisted of adsp21060 - sharc parallel 32 - bit floating point dsp, distributed parallel system and shared bus parallel system will satisfy signal processing tasks in sar application fields. this paper discusses range - doppler ( rd ) algorithm and two - dimension detachable algorithm in the side - looking model in synthetic aperture radar ( sar ) respectively, then studies the realization on multi - chips adsp21060 sharc dsp system
以美國ad公司的adsp21060 - sharc （超級哈佛結構計算機）系列并行32位浮點dsp構成的分散式并行系統和共享總線式并行系統，可以滿足綜合孔徑雷達（ sar ）應用領域的信號處理任務。
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