floating-point unit 中文意思是什麼

floating-point unit 解釋
浮點處理單元
  • floating : adj. 1. 漂浮的，浮動的，流動性的。2. 【醫學】游離的。3. 移動的；不定的。4. （塗工的）第二道（漆等）。5. （船貨）未到埠的，在海上的，在運輸中的。
  • point : n 1 尖頭，尖端；尖頭器具；〈美國〉筆尖；接種針，雕刻針，編織針；小岬，小地角；【拳擊】下巴。2 【...
  • unit : n 1 個體，一個，一人。2 （計值、組織、機構）單位；單元；小組，分部；【軍事】部隊；分隊。3 【機械...
  1. Feu floating point execution unit. this performs floating point related calculations for both existing scalar instructions along with support for some of the new simd - fp instructions

    Feu浮點執行單元。與支持simd _ fp指令的現有規模指令一起執行浮點相關的計算。
  2. Fpu : floating - point processing unit

    浮點處理單元
  3. 2 montoye r k, hokenek e, runyon s l. design of the ibm risc system 6000 floating - point execution unit. ibm journal of research and development, 1990, 34 : 59 - 71. 3 oberman s. floating - point arithmetic unit including an efficient close data path

    我們採用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該演算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且演算法本身沒有造成新的關鍵路徑。
  4. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  5. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  6. This paper studies fpu ' s algorithm, data - path, control - path, and implements the integration of the powerpc603e system. this thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded powerpc603e microrpocessor

    論文的研究工作包括： ?研究浮點演算法，主要包括加減法、乘法、除法、開平方以及cordic （ coordinaterotationdigitalcomputer ）演算法。
  7. Prior to google, alan spent 15 years at digital compaq hp s western research laboratory where he worked on a variety of chip design and architecture projects, including the microtitan floating point unit, bips the fastest microprocessor of its era

    在他加入google之前， alan在digital compaq hp的西部研究室工作了15年，致力於各種晶片的設計及製造專案，其中包括當時最快的微處理器： microtitan floating point unit ， bips 。
  8. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  9. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  10. The work in this thesis was part of a national 05 " project which task was designing the " longtengrl " microprocessor. there are four parts in " longtengrl " microprocessor : integer execution unit ( ieu ), floating point unit ( fpu ), memory subsystem unit ( msu ) and bus interface unit ( biu )

    本論文完成存儲子系統單元的設計與實現、 「龍騰r1 」系統的集成、存儲子系統單元的驗證以及在「龍騰r1 」存儲子系統基礎上進行了tracecache的研究，其中重點討論存儲子系統的設計與實現。
  11. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  12. 3 - d graphics on mobile phones is quite similar to 3 - d graphics on pc in years past. there is no hardware acceleration, and processor speeds are quite low, and there also is the lack of floating point arithmetic unit in mobile phones

    因此論文從通用的部分開始論述，然後明了移動平臺的特徵，並試圖解釋三維引擎的一般原理和設計一個具有粗適性的基於游戲的三維圖形引擎。
  13. Resets the floating - point unit ( fpu ), if any

    有浮點單元（ fpu ）的話，將其重置。
  14. Function ensures the rounding mode of the floating - point unit is toward zero truncate, by setting bits 10 and 11 of the control word

    函數還通過設置控制字的第10位和第11位來確保浮點單元（ fpu ）的舍入模式為向零方向（截斷） 。
  15. On the one hand it is important for the design of floating - point processor unit to optimize speed while algorithms of high - speed are introduced. for examples, two - path of high - speed floating - point addition, booth coding of floating - point multiplication. srt of floating - point division and square root, cordic of transcendental function and so on

    一方面浮點處理部件設計重點在於速度的優化，所以採用優化的高速演算法，如浮點加法的two - path 、浮點乘法的booth編碼、浮點除法和平方根的srt演算法以及超越函數的cordic演算法等。
  16. Floating - point unit is a special microprocessor circuitry unit that deals with floating - point arithmetic operations, which is widely used in scientific arithmetic, cpu, dsp ( digital signal processing ) and image processing, the thesis discusses how to implement high - performance floating - point processing unit based on the research of its implementation algorithm and its implementation structure

    浮點運算單元（ fpu ）是處理器中專門進行浮點算術運算的電路單元，廣泛應用在科學計算、 cpu 、 dsp和圖象處理。論文從浮點運算單元的實現演算法和結構的研究出發，討論如何實現高性能浮點運算單元。
  17. Optimized 32 64 - bit floating - point unit, conforming to ieee - 754 standard

    位浮點處理單元，遵循
  18. The power2 added a second floating - point unit and more cache

    Power2晶元中新加了第二個浮點處理單元（ fpu ）和更多緩存。
  19. According to the task and delay information of the floating - point unit, it was implemented with three - stage pipeline, including pre - normalization stage, calculation stage and post - normalization stage. approximately, the delay of each stage is equal with each other. also, floating - addition, floating - subtraction and floating - multiplication can been implemented by the floating - point unit

    根據浮點單元承擔的任務及延遲信息，採用三級流線實現：前規格化級（ pre - normalizationstage ） 、計算級（ calculationstage ） 、后規格化級（ post - normalizationstage ） ，每一級的工作量和延遲近似相等。
  20. In the project, the microprocessor is composed of integer unit and floating - point unit

    本課題所設計的微處理器共包括兩部分：整數單元和浮點單元。
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