fpu 中文意思是什麼

fpu 解釋
浮點數處理器
  1. Fpu : floating - point processing unit

    浮點處理單元
  2. Improved algorithms for basic arithmetic operations in airborne risc fpu

    中基本算術運算演算法研究與實現
  3. Fpu float point unit

    浮點運算單元
  4. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  5. This paper studies fpu ' s algorithm, data - path, control - path, and implements the integration of the powerpc603e system. this thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded powerpc603e microrpocessor

    論文的研究工作包括： ?研究浮點演算法，主要包括加減法、乘法、除法、開平方以及cordic （ coordinaterotationdigitalcomputer ）演算法。
  6. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  7. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  8. The work in this thesis was part of a national 05 " project which task was designing the " longtengrl " microprocessor. there are four parts in " longtengrl " microprocessor : integer execution unit ( ieu ), floating point unit ( fpu ), memory subsystem unit ( msu ) and bus interface unit ( biu )

    本論文完成存儲子系統單元的設計與實現、 「龍騰r1 」系統的集成、存儲子系統單元的驗證以及在「龍騰r1 」存儲子系統基礎上進行了tracecache的研究，其中重點討論存儲子系統的設計與實現。
  9. To modify the fp control word, then the run - time startup code will set the x87 fpu control word precision - control field to 53 - bits, so all float and double operations within an expression will occur with 53 - bit significand and 15 - bit exponent

    修改fp控制字，則運行庫啟動代碼會將x87 fpu控制字精度控制欄位設置為53位，這樣，表達式內的所有浮點運算和雙精度運算都以53位有效數和15位指數進行。
  10. Resets the floating - point unit ( fpu ), if any

    有浮點單元（ fpu ）的話，將其重置。
  11. Secondly, we numerically simulate the turbulence behavior of one - dimension fpu model and obtain probability density functions of the velocity differences in different conditions. we use tsallis statistics to fit the probability density functions and find out it was fitted very well

    其次，我們對一維fpu模型中類似湍流行為進行了數值模擬，得到不同條件下速度差的概率密度函數，並利用tsallis統計對其進行擬合，發現兩者符合得非常好。
  12. The default rounding mode of the fpu is " round toward nearest. " using

    Fpu的默認舍入模式為「舍入為最接近的整數」 。使用
  13. Select and verify some algorithms of powerpc603e ' s fpu. design and implemention of the data - path of fpu, with emphasis in design a 64bit multiply - add unit. powerpc603e is a complex microporcessor system

    ? fpu中數據通路的設計與實現：重點是一個64bit乘加器的實現，包括部分積產生和選擇單元、 wallace壓縮單元、 161bit加法器。
  14. Based on s698 technology, obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller, etc. the bus interfaces is composed of i2c spi magnetic card interface and ic card interface. obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition

    Obt - devsys - s698是s698系列嵌入式處理器開發板中的一員，其上包括：具有32 64 - bit浮點運算單元的32 - bit嵌入式處理器，主頻160mhz ， sram存儲器， flash存儲器具有三路uart介面，一路ps 2介面， led發光二極體控制電路，中斷操作按鈕其外擴總線包括i2c總線介面spi總線介面磁卡介面智能卡介面等。
  15. When programming for x86 processors, because the fpu is set to 53 - bit precision, this will be considered long double precision

    在為x86處理器編程時，由於fpu設置為53位精度，因此將被視為長雙精度。
  16. C run - time function to modify the rounding behavior of the fpu

    C運行時函數修改fpu的舍入行為。
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