function timing 中文意思是什麼
function timing
解釋
操作計時-
( 3 ) the dissertation designs the hardware diagrams of corelation matrix module and spectrum peak finding module. accroding to the hardware diagrams, the dissertation codes by vhdl and do function simulation and timing simulation
（ 4 ）本文對music演算法的各模塊進行了互連調試工作。當採用了altera公司cyclone系列的fpga實現music演算法時，單次運算時間在20us以內。 -
Inside the instrument has many kinds of scaling conversation formula which can carry out chosen scale conversation such as convert into length etc. digital clock timer wide use to clocking, timing in every industry field. it is operate brief, clocking accuracy, timing alarm, and with outer connected start stop, clear function
本表含有前述智能流量積算控制儀的全部功能，增加了獨特的防盜措施，提高了系統的安全性，即使在斷電的情況下，亦可有效地防止盜用，保證了用戶的準確計量使用，且操作簡便，可靠性高。 -
Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。 -
This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15
該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。 -
Timing wage function and optimal wage - pricing model
計時工資函數與最優工資定價模型 -
Personal data provision, timing and usage methods : if you need to modify your data at a later time, we provide an editing function under the hirecruit member services area. simply follow the instructions on the website to update and manage your profile
二您個人資料的管理及維護：您登錄的履歷表，邇后如有編修開啟或關閉之需，我們提供您自行維護履歷的功能，您可於hirecruit首頁會員區，點選您的身分登入，進入會員服務專區，依照選項逐一進行維護即可。 -
Bits supplies the synchronous timing signal to these equipments inside the telecommunicationt building, such as dps, atm, no. 7, dxc, tm & adm in sdh, don and in etc. the related techniques are involved in the content of synchronization ne twork, timing distribution, the timing signal transportations x impairments etc. the second chapter tells the structure and the function of the building integrated timing system. the third chapter summarizes the digital synchronization network techniques, which emphasizes the basic concept of synchronization networks analyzes the necessity of building the synchronization network and introduces all kinds of synchronization methods. the fourth chapter represents the transportation of the synchronization signal
本文第二章講述了通信樓綜合定時系統的構成及作用：第三章概述了數字同步網技術，著重描述了同步網的基本概念，分析了建立同步網的必要性，講述了各種同步方法；第四章闡述了同步定時信號的傳輸；第五章介紹了bits設備所支持的同步狀態消息；第六章、第七章為本文的重點，通過對時鐘信號建立數學模型，從理論上分析時鐘內部噪聲和相位瞬變產生時鐘定時信號損傷的原理，企圖尋找到更好地控制頻率漂移的方法。 -
After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages
它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。 -
A mathematics model in the form of differential equation was constructed base on the theory of motor timing. then the model was changed into the form of transfer function. with the help of matlab, the model in the form of transfer function can be easily solved
應用交流電機調速理論，建立了船舶電力推進系統的微分方程形式的數學模型，再將其轉化為傳遞函數形式的數學模型，應用matlab語言進行了動態特性模擬計算。 -
After introduction of the whole fpga design of b3g downlink, chapter four schemed out every function module such as time synchronization, frequency synchronization, timing recovery, last frame detect, ofdm demodulation and rocket i / o interface etc. lots of structure schemes and simulation waves were presented
主要包括時間同步模塊、頻率粗同步模塊、頻率精同步模塊、定時恢復模塊、尾幀檢測模塊、 agc / afc輔助模塊、 ofdm解調模塊和rocketi / o介面模塊等。 -
To study the periodical electromagnetic pulses with random timing jitter radiated by electromagnetic pulse transmitters, the psd ( power spectral density ) of periodical electromagnetic pulses with random timing jitter was obtained based on the analysis of the - function of the psd of timing jitter
摘要針對工程實踐中電磁脈沖發射機輻射的隨機時間抖動周期性電磁脈沖信號，在分析隨機時間抖動周期-函數功率譜密度的基礎上，得出了隨機時間抖動周期性電磁脈沖串的功率譜密度。 -
It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。 -
" function, the user can record behavior directly in the field by setting the time interval through the audio alarm function for time sampling of behavioral data. if the behavior is recorded on videotape, this program can also match its timing with the timing recorded on the videotape or the vcr counter, and the user can correct data directly or press a special key to perform editing functions corresponding to the vcr, including pause for timing, different playback speeds, and modifying previous records. users can also continue recording data from previously saved data in the
在記錄數據功能上，可直接在現場記錄，也能夠配合時段采樣的時間間隔使用鬧鈴功能，也可以配合所拍攝錄影帶上的時間（或錄影機上顯示之時間）做同步記錄；修改功能方面，提供直接按鍵修改或按特殊功能鍵以配合錄影機的特殊功能，包括暫停，不同播放速度和連續多次修改記錄；可選擇單鍵即時記錄 -
On the basis of investgation on the related literature of electronic speed governor at home and abroad, this proper control parameters are obtained through the experimental research of the pid digital control parameters with the orthogonality method and through the analysis of the speed change of gasoline engine rev. the electronic speed governor designed hereby performs its controlling fuction through programs, the stable rev and static timing rate of which are also set and controlled by software, has, therefore large universality and function flexibility. so for different types of gasoline engines, the obtainment of relevant parameters and the designing of relevant programs suffice to realize the control functions of the electronic speed governor
本文在分析研究國內外有關電子調速器的基礎分析方法及其研究狀況的基礎上，採用pid數字控制，並用正交試驗方法對pid數字控制的控制參數進行試驗研究，得到了合適的控制參數。所設計的電子調速器是靠控制軟體來實現調節和控制功能，穩定轉速、穩定調速率等都可以進行程序設定控制，具有很強的通用性和功能擴展能力。對不同型號的汽油機，只要經試驗取得合適的控制參數，編制出相應的控製程序，就可以使用此電子調速器進行轉速控制。 -
By using the method, 6, 8, 10, 2 and 4 cam - linkage mechanisms are deduced from the 2 existing six - bar kinematic links in order to accomplish function, motion trace, trace, plane motion refer to timing and plane motion regardless of timing respectively. and 48 cam - linkage mechanisms are deduced form the 16 existing eight - bar kinematic links to accomplish plane motion refer to timing. the method is also useful in multibar kinematic links ’ transformation and helpful in developing new cam - linkage combined mechanisms
並採用此方法，對現有的2種基本型式的六桿運動鏈進行轉換，得出6個實現函數、 8個實現運動軌跡、 6個實現軌跡、 2個實現平面運動1和4個實現平面運動2的凸輪連桿組合機構;對16種基本型式的八桿運動鏈進行轉換，得出48個實現平面運動1的凸輪連桿組合機構。 -
Its premise is pci bus specification and its sticking point is to analysis the function and architecture of pci bus controller. this dissertation finishes the design of pci bus controller, and it has also completed the function simulation of this module as well as timing simulation and a pcb card for test which prove it rightness at last
通過本論文的研究，完成了pci總線控制器的設計，並且通過編寫測試激勵程序完成了總線控制器功能模擬，以及布局布線后的時序模擬，並設計了pcb實驗板進行了測試，證明所實現的pci目標控制器完成了要求的功能。 -
Then describes the 4 function modules in vhdl, the vhdl programs have passed compile and debug in maxplus ii, the results of function simulation and timing simulation all prove that the design is correct, at last, maxplus ii generates a netlist file which can be download into chip
然後使用vhdl硬體描述語言對四大功能模塊進行描述，在maxplus環境下編譯、調試通過，功能模擬和時序模擬結果證明設計正確，最後生成可下載的網表文件。 -
Then has analysed function 、 port joining 、 inside structure of every module, etc. in detail. using hardware description language to program for function implementation, after function simulation 、 synthesis 、 place and route 、 timing simulation and download, the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xilinx. all procedure of design is worked under the ise 6. 2 integrated environment
接著詳細分析了各模塊的功能、埠連接、內部結構等，並利用硬體描述語言編寫源代碼實現各模塊功能，經過功能模擬、綜合、布局布線、時序模擬、下載等一系列步驟，最終在xilinx的spartan3系列xc3s400 - 4pq208晶元上實現。 -
This paper briefly introduces design method of the multi - function timing control unit. it is made of 89c51 and other integrate circuit chip, and produce the frame diagram for monitoring program
摘要介紹了一種多功能定時控制器的設計方法。它是由89c51單片機和幾個主要的集成電路晶元構成。並給出了監控軟體的結構框圖。 -
The computer mainly realizes the functions of long - range supervision and management and it includes : real time data communication, running state monitoring, history data save and print, error alarm, etc ; the industry computer system mainly compulish data acquisition and signal setting during the experiment and finish data storage and management ; the plc control system mainly accomplishes the on - off input and output, it accomplishes timing control, checks the status and carries the over - voltage and over - current protection ; except for acquiring experiment data, intelligent control instruments also have the function of errors diagnose and communication
上位計算機的任務是實現遠程監測和管理，主要進行實時數據通信、運行狀態監視、歷史數據存儲與列印、故障報警等；下位工業控制計算機主要用於實驗數據採集和參數預置； plc控制系統主要完成開關量和部分模擬量的輸入輸出，實現系統運行的時序控制狀態巡檢和過載保護；智能監控儀器除獲取現場參數外，還具有故障之診斷和通信功能。
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