gate array 中文意思是什麼

gate array 解釋
門數組
  • gate : n 1 大門，扉，籬笆門，門扇。2 閘門；城門；洞門；隘口，峽道。3 【冶金】澆注道，澆口，切口；【無線...
  • array : vt 1 打扮，裝飾。2 使…列隊，排列。3 提出（陪審官）名單，使（陪審官）列席，召集（陪審官）。n 1 整...
  1. This thesis primarily discussed the baseband processing of ss communication signal based field programmable gate array ( fpga ) asic chip

    本論文主要討論和實現了基於fpga的擴頻通信信號的基帶處理。
  2. After the investigation of the general technology of hardware implementation, how to implement the kasumi algorithm using field programmable gate array ( fpga ) device is discussed in detail, and the author develops the cipher chip of kasumi algorithm, the kasumi cipher card based on 32 - bits pci bus, the wdm device driver that used in windows2000 / xp, and the software to demostrate encrypting data link. finally, an application demostration is constructed with all the above implementation

    在此硬體實現的結果晶元基礎上，設計了32位的基於pci總線的kasumi加密卡，編寫了windows2000 xp下的windows驅動程序模型（ wdm ）驅動程序和鏈路加密應用程序，由此構成一個應用演示系統，作為研製結果的應用評估，為進一步進行第三代移動通信系統相關安全技術研究和開發提供了基礎條件。
  3. In this paper, the method of digital evolvable hardware is studied based on the dynamical reconfiguration of field programmable gate array ( fpga ). in the paper, firstly, the basic conception and theory of ehw are roundly introduced and the structure characters of ehw chip are analyzed. secondly, the thought of standard evolutionary algorithm is discussed and the flow of improved evolutionary algorithms is analyzed

    本文首先較全面地介紹了硬體演化技術的基本概念和原理，分析了演化硬體晶元的結構特點；其次，討論了標準演化演算法的思想並對改進型演化演算法的流程進行了分析；然後著重分析了演化硬體實現中的關鍵技術，對其實現方案進行了深入的研究，文中分別採用外部演化和內部演化兩種方式對不同的應用電路進行了演化。
  4. Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises

    3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。
  5. We first design the construction modules of serially concatenated quantum convolutional code. and then design the corresponding code - coding gate - array. in quantum error avoiding code, we first unified the definitions of decoherence - free subspace, and then proved that all these definitions are equivalent

    在量子避錯碼方面，統一了各種無消相干子空間的定義，證明了各種定義之間的等價性，同時提出一種利用群論方法構造無消相干子空間的簡單方案。
  6. The digitizer based on pxi bus uses fpga ( field programmable gate array ) to implement 256 points, radix - 2 dit fft ( fast fourier transform algorithm ). the design uses pipelining for fft processing and can accomplish sampling and processing signals of two channels at the same time. in the signal acquisition circuit, - a / d convector is used to enhance the precision of the signal sampling

    在本設計中，採用fpga （ fieldprogrammablegatearray ）實現了256點基2dit演算法復數fft （ fastfouriertransformalgorithm快速傅氏變換演算法）處理器，具有較高的速度和運算精度fft ，設計採用流水線處理方式大大的提高了處理速度，可實現對兩個通道輸入信號的并行採集與處理。
  7. Application of field programmable gate array in biomedical engineering

    現場可編程門陣列的生物醫學工程應用
  8. The method of design of system on chip ( soc ) based on the field program gate array ( fpga ) is also introduced

    並對課題中採用的基於現場可編程門陣列（ fpga ）的片上系統（ soc ）設計方法進行了介紹。
  9. With the quickly development of field programmable gate array, fpga with more than million logic gates has been used

    隨著fpga （現場可編程門陣列）技術的快速發展，萬門以上乃至幾十萬門邏輯陣列的使用越來越普遍。
  10. Through some research in depth on soct, this thesis proposes a scheme of star - type vsat ( very small aperture terminal ) network based on overlap back transmission, and do some research on key techniques involved with the scheme and their partial realization with fpga ( field programmable gate array ), such as spread spectrum techniques, a non - coherent de - spreading spectrum and demodulation technique and adaptive interference cancel

    本文在深入研究衛星重疊通信技術的基礎上，提出了一種基於重疊回傳的星形vsat網方案。並在衛星重疊通信涉及的幾種關鍵技術及其部分核心器件的fpga實現等方面進行了一些研究，包括：擴頻技術、非相干解擴解調技術、自適應干擾抵消技術等，並將它們用於基於重疊回傳的星形vsat網方案。
  11. The circuit is based on the conventional delay - superposition algorithm realized by the field programming gate array ( fpga ). the circuit makes it possible to deinterleave and track with pri in real time

    本文還利用fpga對重頻跟蹤電路進行了設計，根據延遲重合法提出一種新的實現方案，由於不用進行首脈沖的確定，使得實時跟蹤成為可能。
  12. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory. in 1995, barenco showed that almost any two - bit gate is universal, so building a feasible two - bit logic gate is the first step to engineer a quantum computer. in principle, the quantum bit can be carried by any two states system

    在眾多的量子計算機模型中目前討論最廣泛的是量子計算機門組網路模型，量子計算機門組網路模型是經典計算機門組網路結構的量子推廣，它是根基於barenco等人所證明的「一個兩比特受控操作和對單比特進行任意操作的門可以構成一個『通用量子邏輯門組』 」之上的。
  13. In this study, the design procedures for mitigating radiation effects mechanisms have been implemented in a gate array design, we have obtained samples of integrated circuits test structures manufactured by wuxi csmc - hj using their 0. 6 - m cmos process

    在研究中，我們將降低輻射效應的設計方法應用到門陣列設計中，獲得了華晶上華半導體有限公司採用0 . 6 m的cmos工藝生產的集成電路樣片，具有100krad （ si ）的抗總劑量輻射能力。
  14. To realize the real - time tracking image target, we use the cpld ( c ' omplex programmable logic device ) to control the system logic and use ipga ( field programmable gate array ) to preprocessing the image

    為了滿足系統的實時性要求，運用大規模可編程邏輯陣列cpld進行邏輯控制和現場可編程門陣列fpga對採集的視頻圖像做預處理。
  15. And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time

    其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。
  16. Gate array design generals for semiconductor integrated circuits

    半導體集成電路門陣列設計總則
  17. In this dissertation, the method to design and realize the digital receiver in the field programmable gate array ( fpga ) has been discussed ; combining coordinate rotation digital compute ( cordic ) to design nco, we get a efficient structure without multiplications

    本論文正是運用現場可編成邏輯器件（ fpga ）設計與實現數字接收機問題開展研究，結合坐標旋轉數值計算（ cordic ）演算法實現數控振蕩器（ nco ） ，得到一種免乘法器高效可移植性好的數字接收機fpga實現結構，並在現有的硬體平臺上進行了接收機系統的調試，測試結果表明該接收機能夠達到系統指標要求。
  18. Fpga ( field programmable gate array ) is a kind of programmable logic device

    Fpga屬於一種可編程邏輯器件，晶元內部以陣列狀排列各種可配置邏輯塊。
  19. The system used hight - performance dsp ( tms320c6202 ) to realize the real - time image object tracking algorithm, used large - scaled programmable logical array cpld to control logic and field programmable gate array fpga to preprocessing the image

    其中運用了高性能dsp （ tms320c6202 ）完成實時圖像目標處理演算法，並結合大規模可編程邏輯陣列cpld進行邏輯控制和現場可編程門陣列fpga對採集的視頻圖像做預處理，滿足了系統的實時性。
  20. For the high - speed digital signal processing, the structure of fpga and dsp is widespreadly adopted. dsp is more featured in the implementation of complicated algorithm, while field programming gate array ( fpga ) shows more advantage in its flexibility of design, simplicity of system configuration, modification and maintenance. in the paper, the hardware system of the spaceborne radar is based on the structure of fpga and dsp, of which the signal processing part is accomplished with one fpga chip and multi dsps

    Dsp適合完成結構復雜的演算法;現場可編程邏輯陣列（ fpga ）適合完成高效、演算法固定的任務;與專用集成電路（ asic ）相比， fpga優點主要在於其很強的靈活性、可在線配置、修改和維護方便等優點。本文工程中的星載雷達信號處理和控制系統就是採用dsp + fpga的方式。其中信號處理採用的是xilinx公司的virtex -和virtex系列fpga和多片analogdevices公司的tigersharcts101的硬體電路結構。
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