generator clock 中文意思是什麼
generator clock
解釋
時鐘產生器-
Clock - pulse generator
時鐘脈波發生器 -
Real - time power angle measurement of a synchronous generator based on gps clock signal and tachometer
時鐘信號的發電機功角實時測量方法 -
The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation
再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。 -
As is known to all, the former pcb system uses an out - chip oscillator, which is called out - chip clock generator, to provide system with clocks
比如以前的板極系統多數使用電路板上的外部振蕩電路作為系統的時鐘發生器。 -
High - frequency clock generator based on dds hybrid pll
基於鎖相混頻原理的高精度激光外差干涉信號的處理方法研究 -
The following is main content of our thesis. the first, we analyze the system operation theory of cmos image sensor with pixel level adc ( a / d converter ). it is made up of three sections : pixel array, clock signal generator and sam ( sequential access memory )
本文的主要內容如下：首先，我們對像素級a d轉換型圖像傳感器的系統工作原理進行了分析，是由像素陣列、時鐘信號產生器和sam （順序讀寫存儲器）三部分構成的。 -
The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions
本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。 -
The adm system mainly includes a oscillator, a clock generator, an amplifier, a pre - amplif ier, a comparator, an agc ( automatic gain control ), an adm analyzer & synthesizer, a d / a converter and a lowpass filter
整個系統包括：內置振蕩器，時鐘產生器，放大器，前置運算放大器，比較器， agc （自動增益控制器） ， adm分析綜合器，數模轉換器以及低通濾波器。 -
The signal collecting system of singlechip collects the signals from generator. the paper introduces the every part of the singlechip. the key component is a 8051cpu, its surrounding circuits include dc power source, simulating signal collecting circuit, digital signal collecting circuit, a / d converting circuit, clock generating circuit, counting frequency circuit, controlling circuit, communicating circuit, and some other circuits
前臺單片機採集系統完成對發電機組多信息量的採集，本文詳細介紹了電路設計，系統的核心器件為8051cpu ，其外圍電路包括電源電路、模擬信號採集電路、 a d轉換電路、數字信號採集電路、時鐘發生電路、測頻電路、控制電路、通訊電路等。 -
Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method
該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號，用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率，而且這一調頻過程幾乎是連續的（實際上是眾多離散點構成的線性近似） 。 -
In the parts of software discussion, it presents the primary algorithms of some fundamental functions in c language, these functions are developed for digital i / o operations, interruption management, tinier management, precise clock generator
同時，解決了在采樣過程中，大量數據的快速轉存。編寫了實現上述功能的c語言程序。論文中還介紹了數字信號處理在系統檢測中的應用。 -
The sampling clock generator must also have adequate spectral purity
時鐘發生電路固有的抖動應該足夠小。 -
Ieee j. solid - state circuits, 2003, 8 : 689 - 695. 10 alvandpour a et al. a 2. 5ghz 32mw 150nm multiphase clock generator for high - performance microprocessor
模擬結果顯示，在0 . 18m cmos工藝下，這種加法器的延時為485ps ，平均功耗僅為25 . 6mw ，達到了高速低功耗的目標。 -
The implementation of in - chip clock generator is often based on modern cmos ic process technology which is usually adopted by very large scale digital system. while designing a deep sub - micrometer cmos circuit, delay, power consumption and die size are of the main factors that must be considered
使用現代深亞微米cmos集成電路工藝製造的內部時鐘發生器要綜合考慮延時、功耗、面積等各種重要因素，而且經常要針對soc系統的需求設計特殊的電路結構。 -
Based on the characteristic structure of clock controlled combined generator, this paper construct probability model of the stop - and - go generator, kmm combined generator, km1m2 combined generator, additive combined generator, as well as the combined generator constructed by three " stop and go " generators
本文依據鐘控組合生成器的結構特徵，建立了「停走」生成器、 km （ ? ）型組合生成器、 km _ 1m _ 2型組合生成器、加法型組合生成器以及由三個「停走」生成器組合而成的生成器的概率模型。 -
These settings control how often data is processed, how far the generator is allowed to fall behind the real - time clock, how events are processed, how much data can be received and sent, how distribution data is logged, and how often old data is removed from the database
這些設置控制處理數據的頻率、允許生成器滯後於實時時鐘的程度、處理事件的方式、可以接收和發送的數據量、記錄分發數據的方法以及從數據庫中刪除舊數據的頻率。 -
These settings control how frequently data is processed, how far the generator is allowed to fall behind the real - time clock, how events are processed, how much data can be received and sent, how distribution data is logged, and how frequently old data is removed from the database
這些設置控制處理數據的頻率、允許生成器滯後於實時時鐘的程度、處理事件的方式、可以接收和發送的數據量、記錄分發數據的方法以及從數據庫中刪除舊數據的頻率。 -
In order to make full behavior simulation of sigma - delta modulator, the noise models have been set, taking into account most of the sigma - delta modulator ’ s non - idealities and the final result supports the noise models. last, the main circuits of modulator have been designed, such as operational amplifier, comparator and clock generator, the design principle of noise - killed logic circuit has been presented. these circuits have been simulated
調制器的噪聲模型，考慮了影響調制器性能的一些主要非理想因素，通過模擬驗證了噪聲模型的正確性;最後，設計實現了結構中的主要電路，如運放、比較器、時鐘產生電路，闡述了噪聲抵消邏輯電路的工作原理，利用hspice和cadencespectre對各電路進行了模擬，驗證其功能。 -
Advanced multi - clock mechanism and clock generator
先進的多時鐘機制和時鐘發生器 -
Irig - b clock code generator in gps timing
時間碼產生器設計
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