hardware design language 中文意思是什麼
hardware design language
解釋
硬體設計語言-
In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical
在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。 -
The key to the fft algorithm is the design of butterfly computation and that of the address logic. the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ), basing on these, we do our research on reconfigurable technology. the result indicates that the data processing ability of reconfigurable system improved greatly
結果表明，可重構系統在數據處理能力方面比以往的系統有了很大的提高，本設計實現的fft重構處理器可工作於60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構性，可以方便地將其運算點數進行擴展，或將其他的圖像處理演算法在實時處理系統中實現。 -
Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises
3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。 -
In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools
本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。 -
As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost
所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。 -
The methods of adopting fpga to realize the function of counter, and adopting verilog hdl hardware description language to design every function modules, not only makes the whole design more compact and stable, but also make the alteration of the circuit ’ function merely need to alter the software according to the practical task requires, and needn ’ t alter the hardware connection of the circuit
在計數器功能的實現上採用fpga （ fieldprogrammablegatearray ） ，利用veriloghdl （ hardwaredescriptionlanguage ）語言編寫了各個功能模塊，不僅使整個設計更加緊湊、穩定且可靠，而且可以根據實際的任務要求，在無需改變硬體電路板的情況下，通過修改硬體描述語言程序，即可修改電路功能。 -
( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching
（ 2 ）對基於32位mips架構雙發射流水線的指令發射策略、控制相關處理和數據相關處理等流水線結構的重要問題進行深入研究，並得出了靜態發射、優化編譯指令序、第一流水線無延遲分支處理和雙流水線四通道前向數據通路等一系列能夠與32位mips架構相匹配的雙發射流 -
Becausc of using the advanced dsp, popu1ar high speed pci bus and laxge scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree
由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得本設計的整個系統具有相當的水平。 -
Because of using the advanced dsp, popular high speed pci bus and large scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree
由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得整個系統具有相當高的數據處理能力。 -
Electronic design hardware description language vhdl
電子設計硬體描述語言vhdl -
This paper introduces the hardware design of the high speed data acquisition system based on scm and fpga, provides the connecting scheme of the circuit, and points out the flow chart and design language of this system
介紹了基於單片機和fpga的高速數據採集系統的硬體設計，提供了電路圖的連接方案，指出了系統的流程圖和設計語言。 -
The second chapter describes the hardware design of the protocol converter that is based on the rabbit 2000 microprocessor. in the third chapter, the software design method of the protocol converter that is developed by the dynamic c language is presented in detail. the fourth chapter is the experiment and applications part
第二章對基於rabbit2000微處理器開發設計的用以完成rs232串列通訊埠協議與tcp江p協議協議轉換功能的協議轉換器的硬體設計進行了詳細描述，第三章對採用dynamicc語言開發設計的協議轉換器的軟體設計進行了詳細描述。 -
The feature of cvi programming language and hardware design is also introduced in detail with some chapters
本文對加載系統所用編程軟體cvi及軟硬體設計特點也進行了詳細的介紹。 -
In this article, we study the implemetation of fpga for elliptic curve digital signature algorithm. based on number thesis 、 abstract algebra and complex thesis ， integrated information theory 、 cryptography and some specific relevant algorithm ， we ascertain the implementation of ecdsa for hardware project ： according to the design idea of hiberarchy and modularization, we adopt very high speed ic hardware description language ( vhdl ) as design input and simulate the design in every level and every model for the correct of the fundamental design. after finish the top design, we perform the whole simulation. then ， we carry out the timing simulation after the logic synthes and layout
本文從實際應用出發，研究了橢圓曲線數字簽名演算法的fpga的實現：以基本的數論理論、抽象代數和復雜度理論為依據，結合信息論、密碼學的一些知識以及一些具體的相關演算法，確定了ecdsa的硬體實現方案：按照層次化、模塊化的設計思想，採用硬體描述語言vhdl作為設計輸入進行ecdsa的硬體設計；在每個設計層次和每個模塊都進行了模擬驗證，得以保證底層設計的正確性。在確保每個模塊的設計正確后，完成對電路的頂層設計，進行總體的模擬。 -
In this method, the mems design flow from the system level to device and process level was established and proved by the design of micro gyroscope. in the system level, the system modeling characterized by multi - discipline was simplified and solved by lumped - parameter modeling and nodal analysis method. the mems component library was constructed through analog hardware description language
首先，針對mems系統級設計的多學科交叉的特點，提出了以集中參數建模方法解決mems系統的功能建模，以節點分析法解決不同功能元件的結構實現，以混合信號硬體描述語言作為系統建模和模擬的基礎，並以此建立mems元件庫。 -
The permanent magnet brush - less motor is driven effectively by selecting the bootstrap components properly and dealing with the parasitics correctly. the software design is composed of c language for dsp and vhdl ( high speed hardware description language ) for cpld
設計了基於功率mosfet和柵極驅動晶元ir2130的功率驅動電路，通過對驅動電路自舉元件的合理選擇以及寄生效應的正確分析和處理，實現了無刷直流電機的高效驅動。 -
The hardware circuit boards are produced by a laser photoplotter according to the gerber files gererated from the schematic ( sch ) documents and the printed circuit board ( pcb ) documents. the cplds, programmed with the verilog hardware description language ( verilog hdl ), were completed after four steps : design, simulation, synthesis and fit. the software is developed with c language using direct i / o to communicate with the device through the isa bus computer interface
其硬體電路由專業軟體設計出原理圖sch和印刷電路圖pcb生成，再gerber文件，然後光繪而成， cpld晶元編程（採用硬體描述語言veriloghdl ）經過設計、模擬、裝配、下載完成，高級軟體編程採用c語言i / o方式利用isa總線介面與外設進行通信。 -
Then has analysed function 、 port joining 、 inside structure of every module, etc. in detail. using hardware description language to program for function implementation, after function simulation 、 synthesis 、 place and route 、 timing simulation and download, the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xilinx. all procedure of design is worked under the ise 6. 2 integrated environment
接著詳細分析了各模塊的功能、埠連接、內部結構等，並利用硬體描述語言編寫源代碼實現各模塊功能，經過功能模擬、綜合、布局布線、時序模擬、下載等一系列步驟，最終在xilinx的spartan3系列xc3s400 - 4pq208晶元上實現。 -
Systemc is a system level design language which can be used efficiently in hardware / software co - design and co - simulation. it extends the abilities to describe hardware systems in the basis of c + + language
Systemc是一種適合於進行硬軟體協同設計和模擬的語言，它在c + +語言的基礎上擴充了硬體系統的描述功能。 -
Introduce the characters of fpga and vhsic hardware description language, design the fast walsh - hadamard transfer on the epf10k30 chip, analyze the problems brought by the improper parts of the program design and give the solution
介紹fpga和vhdl語言的特點，設計快速沃爾什?哈達馬變換在可編程器件epf10k30晶元上的實現過程，並對軟體設計中的產生問題進行了分析，研究出解決的辦法。
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