high density chip 中文意思是什麼

high density chip 解釋
高密度晶元
  • high : adj 1 高的〈指物,形容人的身高用 tall〉;高處的;高地的。2 高級的,高等的,高位的,重要的。3 高尚...
  • density : n. 1. 稠密;濃厚。2. 【物理學】濃度;密度;比重。3. 愚鈍,昏庸。
  • chip : n 1 碎片,削片,薄片;碎屑;薄木片;無價值的東西。2 (陶器等的)缺損(處)。3 (賭博用)籌碼;〈p...
  1. Shorts between metal runners are important only in those regions of the chip with a high density of closely packed metal runners.

    金屬布線間的短接,僅在那些具有高密度密集封裝型金屬布線的晶元中才極為重要。
  2. The key stage of fabricating gene chip is pretreatment of glass surface including the processes of nh3h2o treatment, aminosilane treatment and aldehyde treatment. the pretreatment can grow active group that can bind probe effectively on the surface of glass slide. as a result, the actively treated glass slide can suit for fabricating in - situ synthesis high density gene chips

    基因晶元制備技術的關鍵步驟是玻片表面預處理,即對玻片表面進行羥基化、氨基化和醛基化處理,使表面生長的活性基團能有效固定寡核苷酸探針,以滿足原位合成高密度基因晶元對玻片的要求。
  3. The accelerometer which has simple fabricated process and high sensitivity and small parasitic capacitance and residual stress is hybrid integrated with the interface circuit using ic nude chip. so the density of the package is increased, and the noise of the sensing system is decreased. these found the base of capacitive accelerometer module using the mcm method

    該傳感器製作工藝簡單,靈敏度高,支撐梁採用u型,減小了刻蝕后的殘余應力,用玻璃作為襯底,減小了襯底和硅可動質量塊間的寄生電容,且把傳感器晶元和用ic裸片製作的介面電路集成在一起,提高了封裝密度,減小了傳感器系統的噪聲,為採用mcm技術製作電容式加速度傳感器模塊打下了基礎。
  4. Silica ( sio2 ) is a very promising material used to fabricate the optical waveguide for its low insertion loss, efficient fiber - to - chip coupling, high integration density and compatibility with microelectronic process. it is possible to realize the monolithic integration of optical devices with microelectronic devices and the passive devices with the active ones

    而硅基氧化硅光波導以其低的插入損耗、能有效的與光纖耦合、集成密度高、可以充分利用現已成熟的微電子技術等特點成為較為理想的實現波導結構的材料。
  5. As an advanced package, 3 - d stacked csp assembly provides significant size and performance advantages than traditional single chip package. meanwhile, high packaging density tends to generate more power in a package and cause serious thermal problem

    三維疊層晶元尺寸封裝( stackedchipscalepackage )是目前最先進的微電子封裝形式之一,具有體積小、重量輕、封裝效率高等特點。
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