high-speed circuit - switched data 中文意思是什麼
high-speed circuit - switched data
解釋
高速線路交換數據-
As a new interface caters for rapid development of computer peripheral equipment, universal serial bus ( for short usb ) dispels astriction of communication through traditional serial port and parallel port. it is very suitable for real time image data transmission, which requires high speed. this theme describes two - circuit systems, which utilize usb interface to data from a digital image sensor to pc
為了迎合計算機上設的快速發展以及消除計算機外設通過串、並口的通訊的局限性，出現了新的計算機外設介面usb （通用串列總線） ，這種新型介面對于實時的視頻傳輸很適用，本文設計了兩套電腦眼基於ez - usb2131q的usb介面系統。 -
On one hand, the focal point that the interface circuit is designed lies in lining up the arrangement of the aerial data, have adopted one pair of ports ram to cooperate with the counter and realize the lining up of the data, on the other hand, interface focal point that circuit design transmission of data, part this finish mainly and interface of linkport of dsp, make data transmisst to dsp processor at a high speed, go on follow - up punish
一方面，介面電路設計的重點在於對天線數據的整理排隊，採用了雙埠ram配合計數器實現數據的排隊，另一方面，介面電路設計的重點是數據的傳輸，這部分主要完成和dsp的linkport的介面，使數據高速傳給dsp處理器，進行后續處理。這個項目按照自上而下的設計流程，從系統劃分、編寫代碼、 rtl模擬、綜合、布局布線，到fpga實現。 -
After that, the hardware circuit, especially some of the key parts, is investigated in detail. the following processes are also investigated in detail : empoldering the four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data with vhdl ( very high speed integrated circuit hardware description language ) ; empoldering the serial interface and the data collection software in pc with borland c + + builder
接下來詳細介紹了使用vhdl語言開發fpga晶元的細分、辨向、計數、鎖存以及串列傳輸處理等全部功能;用borlandc + + builder開發了pc機上的串列介面、數據採集軟體;設計並製作了fpga晶元及其外圍電路的電路板。 -
The hardware mainly included the emitting circuit of the laser light, receiving circuit and high speed data acquisition circuit
硬體部分包括激光發射電路、回波接收電路，高速數據採集電路等。 -
The high speed mcu c8051f120 includes a multiply and accumulate engine ( mac ) which can be used to speed up mathematical operations, design control, display circuit and process data
選用高性能單片機c8051f120 ，利用其帶有硬體乘法器、運行速度高等優點，設計控制及顯示電路，進行數據處理。 -
As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost
所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。 -
High speed 25 - position interface for data terminal equipment and data circuit - terminating equipment, including alternative 26 - position connector
數據終端設備和數據電路終接設備用的高速25插針介面暨可替換的26插針連接器 -
This system mainly consists of signal generation, high - speed data acquisition, series experimental circuit and corresponding soft
該系統主要由下面幾個部分組成：數字合成（ dds ）信號源、高速數據採集、系列實驗板以及配套軟體等。 -
High - speed serial interface for data terminal equipment and data circuit - terminating equipment
數據終端設備和數據電路終接設備的高速串列介面 -
Secondly, basing on single channel if sr receiver mathematic model, this thesis has designed if sr receiver subsystem and brought forward its design project and system circuit principle diagram, and explained the system working principle. furthermore, this thesis introduces the working principles and respective applications of wideband high - speed adc ad6640, ddc ad6620 and high - speed dsp tms320c6713 according with the if sr receiver subsystem high - speed analog digital conversion department, digital down conversion department and high speed digital signal processing department. thirdly, the thesis emphatically demonstrates the software realization department of the if sr receiver subsystem, which including ad6620 ' s inner parameter software setup, tms320c6713 data transmission and processing and the quadrant demodulation algorithm program realization
其次，基於單通道中頻軟體無線電接收機數學模型，本文設計了中頻（ if ， intermediatefrequency ）軟體無線電接收機子系統，給出了中頻軟體無線電接收機子系統的設計方案和系統電路原理圖，說明了系統工作原理，並分別對應系統中的高速模數轉換部分、數字下變頻部分、基帶數字碩士學位論文軟體無線電理論研究及中頻軟體無線電接收機子系統設計信號處理部分，介紹了高速adcad664o ，數字下變頻器（ ddc ， digitaldownconverter ） ad6620 ，高速數字信號處理器（ dsp ， digitalsignalproeessor ） tms320c6713的工作原理，以及它們在中頻軟體無線電接收機子系統中的應用。 -
In the third chapter, the realizations of the functional circuits are discussed in details such as the realization of the " 200msa / s sampling by parallel adc ", the " high - speed storage of the converted data with different phases ", the " trigger controlling ", the " high - speed transfer by dma " and so on. additionally, the computer simulation of the " data dividing circuit with four different phases ( 0, 90, 180, 270 ) " is given in this chapter
第三章詳細論述「雙a / d并行采樣實現200msa / s采樣」 、 「高速數據流分相存儲」 、 「預觸發采樣控制」 、 「 vc5409與c196hpi通信」 、 「 dma實現高速數據傳輸」等功能電路的實現，詳細說明其工作流程，並給出了關鍵電路? ? 「數據流四相分離」電路的模擬結果。 -
This link may be a high - speed data communication circuit, a local area network ( lan ), a telephone live or a radio channel
這種連接的鏈路可以是高速數據通信電路、局域網（ lan ） 、電話線路或無線通道。 -
In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling
在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。 -
The task in the paper comprises two parts. the software design procedure works as follow, program the drivers for module on pc with cvi, generate the corresponding ddl and then edit the test serial and invoke the ddl by designing soft panel with vc + + 6. 0. thus facilitate users to control module to conduct high speed data test. the hardware design procedure works as follow, design vxi message based interface circuit and plesio - fdc circuit with fast data transport function on xc2vp30, a virtex - ii pro series fpga chip designed by xilinx company which integrates power - pc processor
筆者負責的工作包括軟體設計和硬體設計兩部分:軟體設計是用cvi工具編寫模塊在pc機上的驅動程序，生成動態連接庫，再用visualc + + 6 . 0設計軟面板，實現測試矢量的編輯和動態連接庫的調用，讓用戶很方便地控制模塊進行高速數據測試;硬體設計是在xilinx公司的一片集成了power - pc處理器的virtex - iipro系列fpga晶元xc2vp30上完成vxi總線的消息基介面電路設計和具有快速數據傳送功能的準fdc電路[ 1 ] [ 2 ]設計。 -
This paper introduces the hardware design of the high speed data acquisition system based on scm and fpga, provides the connecting scheme of the circuit, and points out the flow chart and design language of this system
介紹了基於單片機和fpga的高速數據採集系統的硬體設計，提供了電路圖的連接方案，指出了系統的流程圖和設計語言。 -
In this topic, an adc circuit and data - storage system for all digital ultra - wideband receiver was designed, and the ultra - wideband narrow pulse signal that is received is digitalized, using an ultra - high - speed a / d convertor
本課題設計了一個全數字化超寬帶接收器的adc電路及數據存儲系統。利用一個超高速的ad轉換器，對超寬帶窄脈沖信號進行數字化。 -
High ? speed synchronized latch circuit and special clock driver are used, which adapt to the requirement of quick data - transformation with high accuracy and low power
採用高速同步鎖存電路和特殊結構的時鐘驅動電路，在保證精度和功耗設計要求上，實現數據快速轉換。 -
High - speed 25 - position interface for data terminal equipment and data circuit - terminating equipment, including alternative 26 - position connector
數據終端設備和數據電路終端設備包括可選擇26位連接器的高速25位介面 -
Based on the requirement of the data storage of aerospace craft, the purpose of this dissertation is to study the high speed solid - state storage technique interface logic with compactflash card array. the design scheme of a suit of high speed solid - state storage system used with ti " tms320vc5402, lattice " isplsi 3448 and sandisk compacflash card are expatiated. in addition, the paper also gives the material realization scheme of the experiment circuit and interface logic simulation analyzing
本論文以高速cf卡陣列固態存儲技術的介面設計為主要內容，闡述了利用ti公司的tms320vc5402 、 lattice公司的isplsi3448 、 sandisk公司的compactflashcard等組成的高速cf卡陣列固態存儲系統的設計方案，並給出了實驗電路實現方案和介面邏輯的模擬分析。 -
This system combines intelligent measuring instrument with eda and asic design technology, computer hardware and software technology, digital signal processing together. the system hardware includes high - speed data acquisition circuits, analogue signal conditioning circuit, a / d conversion ; fpga circuit with controlling and processing functions and pci interfacing
系統硬體部分主要有模擬信號調理電路和高速a d轉換晶元組成的數字採集電路； fpga組成的控制和數字信號處理電路； pci介面晶元組成的介面電路。
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