in-gate circuit 中文意思是什麼

in-gate circuit 解釋
輸入門電路
  • in : adv 1 朝里,向內,在內。 A coat with a furry side in有皮裡子的外衣。 Come in please 請進來。 The ...
  • gate : n 1 大門,扉,籬笆門,門扇。2 閘門;城門;洞門;隘口,峽道。3 【冶金】澆注道,澆口,切口;【無線...
  • circuit : n 1 (某一范圍的)周邊一圈;巡迴,周遊;巡迴路線[區域];迂路。2 巡迴審判(區);巡迴律師會。3 【...
  1. By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability

    然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點,確定了電流密度比補償型共源共柵結構作為本設計核心電路結構,運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路,改善了核心電路的帶負載能力和電流驅動能力。
  2. During the circuit design, the author analyzed the basic principle of the direct current motor, pwm control, h - bridge power driver, and two control techniques of h - bridge power drive circuit, designed its general structure, so the feasibility of the design is confirmed. then, reference, oscillator, power dmos gate drive circuit ( charge pump, bootstrap ), and dead time generation circuit are designed and analyzed in the sub - circuits. a current - controlled oscillator is presented in this thesis

    在電路設計中,作者介紹了直流電機的工作原理和數學模型、脈寬調制( pwm )控制原理、 h橋電路基本原理和h橋功率驅動電路的兩種控制模式,設計了驅動電路的總體結構,給出了電路的功能模塊,確定了設計的可行性,然後在子電路模塊中,重點分析設計了基準源電路、振蕩器電路、高端功率管柵驅動電路(電荷泵及自舉電路) 、低端功率管柵驅動電路和死區時間產生電路。
  3. Abstract : this paper summarizes flux - gate phenomenon and its composition, and concretely introduces the principle, circuit and applying method in guidance system of pendulum biaxial flux - gate compass

    文摘:文章概述了磁通門現象及磁通門系統的構成,具體介紹了二軸磁通門、羅盤的原理、電路及在導航系統中的應用方法。
  4. The whole part of the data acquisition is build in a computer as two data acquisition cards. they are front card and rear card. the front card composed of four modules. they are : coin circuit module, data flow controller module, sdram array module and system bus interface module. the rear card composed of four odules. they are : asynchronous serial port interface module, adc control odule, ecg signal process module and gate control data produce module

    數據採集模式實現部分的大部分工作是在前面板上完成的,後面板主要是一些外圍電路。前面板採集卡上從物理上來說主要有四塊電路:符合電路,數據流控制器電路, sdram陣列和系統總線介面電路組成。後面板採集卡從總體物理上主要有四塊電路組成: 485串列通信電路, adc控制電路,心電數據處理電路和門控信號產生電路。
  5. The digitizer based on pxi bus uses fpga ( field programmable gate array ) to implement 256 points, radix - 2 dit fft ( fast fourier transform algorithm ). the design uses pipelining for fft processing and can accomplish sampling and processing signals of two channels at the same time. in the signal acquisition circuit, - a / d convector is used to enhance the precision of the signal sampling

    在本設計中,採用fpga ( fieldprogrammablegatearray )實現了256點基2dit演算法復數fft ( fastfouriertransformalgorithm快速傅氏變換演算法)處理器,具有較高的速度和運算精度fft ,設計採用流水線處理方式大大的提高了處理速度,可實現對兩個通道輸入信號的并行採集與處理。
  6. The circuit is based on the conventional delay - superposition algorithm realized by the field programming gate array ( fpga ). the circuit makes it possible to deinterleave and track with pri in real time

    本文還利用fpga對重頻跟蹤電路進行了設計,根據延遲重合法提出一種新的實現方案,由於不用進行首脈沖的確定,使得實時跟蹤成為可能。
  7. In order to enhance the applying efficiency of cl, the cause of premature convergence in binary - coded genetic algorithms ( gas ) is analyzed in this dissertation. the drawback of conventional mutation operator in preventing premature convergence is subsequently pointed out. whereafter, a genetic algorithm, which can be implemented via general logic gate circuit, is proposed

    為了提高計算智能的應用效率,本文分析了二進制遺傳演算法中早熟收斂的成因,指出了傳統的變異運算元在防止早熟收斂方面的不足,提出了一種能有效預防早熟現象的二元變異運算元,並在此基礎上提出了一種便於用常規邏輯門電路實現的遺傳演算法。
  8. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory. in 1995, barenco showed that almost any two - bit gate is universal, so building a feasible two - bit logic gate is the first step to engineer a quantum computer. in principle, the quantum bit can be carried by any two states system

    在眾多的量子計算機模型中目前討論最廣泛的是量子計算機門組網路模型,量子計算機門組網路模型是經典計算機門組網路結構的量子推廣,它是根基於barenco等人所證明的「一個兩比特受控操作和對單比特進行任意操作的門可以構成一個『通用量子邏輯門組』 」之上的。
  9. This paper demonstrates how to generate variable pwm waveform based on standard cpld device, the proposed circuit is incorporated with mcu to provide simple and effective solution for high - performance pwm converters. in the brushless model, the igbt ( isolated gate bipolar transistor ) switch state period table is gained by mc33035 which analyzes the signal of position feed - back

    這部分功能在cpld器件中用vhdl語言開發實現,其isp (在系統編程)方式使得設計與維護都比傳統方法方便靈活,由於逆變器開關元件的觸發信號是由硬體來產生的,因此更容易實現準確的高速實時控制。
  10. In this paper, a three phases high - voltage power mos gate drive integrated circuit has been researched and designed successfully. it is a typical spic, which could be widely used in high power motor control and switching power supply applications. the design goal of the circuit are v0ffset ( max ) is 500v, ia ( m ~ ) is 1 a, the highest frequency of operation ( f ( ~ x ) ) is 100khz

    本文研製成功了一種可廣泛用於大功率電機控制、開關電源等應用中的spic電路?三相高壓功率mos柵驅動集成電路,其設計指標要求為:最高偏置電壓( voffset ( max ) )為500v 、最大輸出電流( i _ o ( max ) )為1a 、最高工作頻率為100khz 。
  11. Usually series mode is used in low frequency circuit while bypass mode is used in high frequency circuit, series mode micro - switch with cantilever structure is similar to an fet, when voltage is applied on gate, and the fet will be turned on between source and drain

    有靜電電壓作用在梁和底面電極時,梁發生偏轉,在源極和漏極之間實現導通,常用於自控和通信系統的信號通路空氣橋旁路開關主要用於微波段信號的通路。
  12. Abstract : constant components and output opened ports in the result of high - level synthesis lead to explicit redundancy in gate - level technology mapping. explicit redundancy can not improve the performance, but increases power consumption, enlarges circuit area and decreases its testability, so it should be removed. this paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability

    文摘:高級綜合結果中常量元件和輸出懸空埠導致門級工藝映射結果中存在顯式冗餘.顯式冗餘無助於提高電路性能,反而增加功耗,降低電路的可測試性,使電路面積增大,應予消除.文中提出了顯式冗餘的隊列循環優化演算法,完全消除了此類冗餘,從而有效地減少了生成電路的基片面積,提高了電路的可測試性
  13. In hardware design, on one hand the internal construction of international rectifier ' s power drive integration circuit are explained. on the other hand the nature and influence of parasitics in the gate drive circuit and the method of bootstrap component selection, which are frequently encountered in this field, are interpreted in detail

    在硬體設計方面,論文對舵機控制器中經常出現的功率器件開關時的高頻干擾和自舉元件選取等問題進行了深入的討論,分析了浮動電壓基準( vs )負過沖的產生機理和危害,提出了具體的解決措施。
  14. Then the operation principle of the device is introduced to the readers and the definition of the limiting rate of the fault current and the compensation degree of the series reactance is done. in this section, the author designs the snubber circuit and the gate drive circuit of the gto

    首先,在總結前人研究成果的基礎上,提出了pwm - fcl的拓撲結構,並對其工作原理進行了闡述,給出了限流度以及補償度的定義,並針對gto的特性,設計了其緩沖保護電路和門極驅動電路。
  15. Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired

    在超導rsfq數字電路模型的理論分析基礎上,論文中採用wrspice對超導rsfq數字電路進行時域模擬,得到了超導jtl傳輸線,緩沖器, rs觸發器, t觸發器,或門等基本邏輯單元電路以及電路參數。
  16. The paper also analyses the dynamic and static characteristic of the hydraulic control circuit and key component used in the hydraulic water gate, such as balanced valve and balancing circuit in the light of special requirement for working condition of the hydraulic water gate used in the three gorges project, and basing on the result from computer dynamic characteristic emulating and by analyzing the technical feature of the balancing circuit in the hydraulic water gate for the three gorges project, quantitatively raises the principle for selection of balanced valve parameter

    論文對液壓啟閉機的液壓控制迴路及其關鍵元件,結合啟閉機工況的特殊技術要求,細致對平衡閥及主要由其構成的平衡閥迴路進行了對比分析。論文對三峽樞紐工程中液壓啟閉機採用的平衡閥,進行了細致的動、靜態特性分析。並根據計算機動態特性模擬的結果,分析了三峽樞紐工程中液壓啟閉機平衡閥迴路的技術特點,定性的提出了平衡閥參數選擇的原則。
  17. Fpga ( field programmable gate arrays ) is a new type of ic ( integrated circuit ) in recent years. it has advantages of compactness 、 economy 、 high speed 、 low consumption 、 full integration and good applicability. it is easy to be developed and be maintained

    現場可編程門陣列器件( fieldprogrammablegatearrays )是近年來嶄露頭角的一類新型集成電路,它具有簡潔、經濟、高速度、低功耗等優勢,又具有全集成化、適用性強,便於開發和維護(升級)等顯著優點。
  18. A distinguishable faults test generation method for digital circuits is presented. the features of basic gate circuits and neural networks are used to establish the test model, and to generate the test patterns for given faults. the fault model and constrained circuit are studied. some strategies, e. g, the reduction of the size of neural network, are proposed in order to accelerate test generation process. the experimental results demonstrate that the algorithm proposed in the paper is effective

    研究一種基於人工神經網路的能區分故障的數字電路測試生成方法,該方法利用電路基本邏輯門的特性和神經網路模型的特點,首先建立測試生成的神經網路模型,然後通過求解網路能量函數的最小值點獲得給定類型故障的測試矢量,其研究結果在可區分故障的測試生成方面提供了一種可能的新途徑
  19. She is located in a chengdu lively ring circuit liang jiaxiang the street intersection, the close neighbor north gate long - distance motor station, is apart from the chengdu train north station only 3 kilometers, is apart from pair of class international airport only 30 minutes vehicle speed, is apart from town center only 10 minutes vehicle speed, the transportation facilitates extremely

    她座落於成都市繁華的一環路梁家巷路口,緊鄰北門長途汽車站,距成都火車北站僅3公里,距雙流國際機場僅30分鐘車程,距市中心僅10分鐘車程,交通十分便利。
  20. Based on the construction of traditional flip - flop, we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock. then this principle is adopted in ternary circuit, a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed

    在二值單閂鎖結構邊沿觸發器的基礎上,把利用時鐘信號競爭冒險的思想應用於三值電路中,提出了基於cmos傳輸門的二值d型時鐘信號競爭型邊沿觸發器。
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