instruction address 中文意思是什麼

instruction address 解釋
指仿地址
  • instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
  • address : n 1 （信上的）稱呼，姓名；地址。2 致辭；寒喧；演說；正式請願。3 談吐，風度。4 〈pl 〉 求愛，獻殷...
  1. If we load this known address, as data, into the program counter, we execute a jump instruction.

    如果我們將已知的地址依數據加載到程序計數器中，就可以執行一條轉移指令。
  2. Instruction details including name and address of beneficiary, name and address of remitter

    指示的詳情包括收款人的姓名和地址匯款人
  3. The addr2line tool which is part of the standard gnu binutils is a utility that translates an instruction address and an executable image into a filename, function name, and source line number

    Addr2line工具（它是標準的gnu binutils中的一部分）是一個可以將指令的地址和可執行映像轉換成文件名、函數名和源代碼行數的工具。
  4. System calls. when an emulator ordinarily encounters a powerpc system call instruction, it emulates the exception by storing the instruction address into the srr0 register, setting some architecture - defined bits in srr1, and transferring control to physical address 0xc00. some powerpc variants allow more control over this behavior, but this is the traditional powerpc model

    當模擬器正常地碰到一個powerpc系統調用指令時，它便將指令地址存入到srr0寄存器，設置srr1中某些體系結構定義的位，並將控制權轉交給物理地址0xc00 ，從而模擬這個異常（有些powerpc的變種允許對這種行為有更多的控制，但是這里的這種是傳統的powerpc模型） 。
  5. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  6. The lk bit specifies whether the address of the next sequential instruction is saved in the link register as a return address for a subroutine call

    Lk位指定了下一個順序指令的地址是否作為子常式調用的返回地址保存在鏈接寄存器中。
  7. The ability to save the address of the next sequential instruction is provided on all branch instructions, including the branch to link register instruction

    所有的轉移指令都具備保存后繼順序指令地址的能力，包括到鏈接寄存器的轉移。
  8. Additionally, a new address translation mechanism and related physical memory management algorithm are presented and analyzed, which hybrid the segment and segment - page addressing. object - oriented instructions are one of the features of jvm instruction set

    另外，文中還提出了一種直接段式和間接段頁式結合的尋址策略和地址轉換技術以及相關物理存儲器的管理演算法，並對這些技術進行了全面的性能評價。
  9. Immediate address instruction

    即時位址指令
  10. Three - address instruction

    三址指令
  11. Zero address instruction

    零址指令
  12. No - address instruction

    無址指令
  13. Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here

    該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。
  14. A method of addressing in which the address part of an instruction contains a relative address

    一種尋址方法，按照這種尋址法，指令的地址部分存放的是相對地址。
  15. An error in these data structures will cause it to execute an illegal instruction or access a non - existent address

    一旦這些數據結構中有錯，就會導致程序執行非法指令或者訪問不存在的地址空間。
  16. The operand entry or subentry in machine instructions that specifies the number of bytes at a specific address that are affected by the execution of the instruction

    機器指令中的操作數項或子項，定義由於執行指令而受影響的特定地址的位元組數。
  17. One - plus - one address instruction

    單階次常式
  18. The current block is the code containing the current location, instruction pointer address

    當前塊是包含當前位置（指令指針地址）的代碼。
  19. Which executes instructions from the current instruction pointer address printing the instruction on the screen until it encounters an instruction that would cause a branch

    ，它執行從當前指令指針地址開始的指令（在屏幕上列印指令） ，直到它遇到將引起分支轉移的指令為止。
  20. N - phus - one address instruction

    加一地址指令
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