instruction architecture 中文意思是什麼

instruction architecture 解釋
指令結構
  • instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  1. 2. researching the cooperation and coordination function of multi - agent, at the same time, particularly analyzing the coordinating principle of multi - agent which was applied in the construction of asphalt concrete road surface, according to the controlling kernel of flowing material and constructing quality ; according as the principle, the course of controlling is actually the course of information streaming, so i respectively introduce the information collecting of different agents in road constructing. at the same time, i introduce the instruction forming of intelligent controlling agent and three kinds of fashions for human being - machine commensalisms, that is cooperation of machine and human agent, architecture of main - machine and assistant - human agent and architecture of main - human and assistant - machine agent, which was applied in different intelligent agent

    對多智能體的協作與協調機制進行了闡述，並對多智能控制主體的以物流和質量控制為核心的瀝青混凝土路面機群施工過程的協調作業原理進行了詳細的分析；基於控制過程是信息流過程的觀點，分別研究了各智能控制主體在路面施工中的信息集成；並在總結了智能控制主體的結構形式及三種人- -機共棲智能控制方式的基礎上，根據本課題的實際，針對不同的智能體，分別確立了不同的控制方式。 3
  2. The dissertation was aimed at a comprehensive instruction and a thorough analysis of aldo rossi " urban architecture theory which based on the study of a number of papers and treatises from overseas and demostic. to induce some exemplariness principles and methods for our design work today

    論文是在參考了大量國內外文獻資料的基礎上，以義大利建築師阿爾多?羅西的城市建築理論及其設計實踐為對象的綜述介紹和分析研究，藉此探討其思想和理論對於我們今天設計工作的指導意義及可茲借鑒的原則和方法。
  3. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。
  4. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  5. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  6. On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology

    本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。
  7. System calls. when an emulator ordinarily encounters a powerpc system call instruction, it emulates the exception by storing the instruction address into the srr0 register, setting some architecture - defined bits in srr1, and transferring control to physical address 0xc00. some powerpc variants allow more control over this behavior, but this is the traditional powerpc model

    當模擬器正常地碰到一個powerpc系統調用指令時，它便將指令地址存入到srr0寄存器，設置srr1中某些體系結構定義的位，並將控制權轉交給物理地址0xc00 ，從而模擬這個異常（有些powerpc的變種允許對這種行為有更多的控制，但是這里的這種是傳統的powerpc模型） 。
  8. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  9. Other differences lie in the instruction set, internal architecture, and control signals.

    其他差別是在指令系統，內部結構和控制信號方面。
  10. This thesis makes use of instruction split, delay - slot scheduling and peephole optimization in porting. the new cross - compiler system, zltcg, not only supports the new target but also absorbs the old system ' s advantages on code optimization and portability. at first, this thesis describes the developing history and theories of compiler, especially on its architecture, bootstrapping and porting

    本文根據新目標機的特點，利用了指令拆分，延時槽調度，窺孔優化等技術，既實現了對新目標機的支持，又吸收了原有系統高度優化和可移植的優點。
  11. The armp, which is controlled by a pipeline mechanism, has excellent real time performance and supports precise interrupt. the armp is compatible to powerpc 603e instruction set architecture ( isa ), and will be implemented by 0. 25 m cmos technique

    該處理器具有自主版權，採用自主設計的流水線結構進行控制，具有優良的實時性和精確中斷的特點，在指令集上與powerpc603e指令集完全兼容。
  12. Specifies the target architecture instruction set

    指定目標體系架構的指令集。
  13. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。
  14. This architecture became known as risc reduced instruction set computer

    這種體系結構稱為risc （精簡指令集計算機） 。
  15. Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer

    超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。
  16. The architecture of the kiosk ? based on a wall instead of a room ? made instruction or collaboration difficult

    而且這種電腦亭是靠墻而立，並非設在房間里，因此很難進行指導工作，使用者也無法彼此合作。
  17. It aims at reducing the number of execution cycles of instructions, and has experienced from the period of single issue architecture to the period of multiple issue architecture. in the past twenty years, risc has become more and more mature abroad. it makes great sense to develop our own risc and it is a effective way to develop our own risc with the instruction set which is compatible with those of risc which has been widely used

    80年代初出現的risc技術是計算機體系結構的重大變革，它以減少指令執行的平均周期數為結構設計的主要目標，經歷了從單發射結構到多發射結構的演變過程，解決了深度流水技術、相關技術、轉移預測技術、編譯優化技術等一系列技術難點，在20多年的時間里， risc技術的發展已日趨成熟與完善微處理器在軍事和民用領域都有著廣泛的應用，研製具有我國自主獨立版權的微處理器在當今具有重大意義。
  18. Based on analysis, we finished the architecture design and the division of the functional modules. allowing for the pic16c57 mcu can not suit the high speed situation, we improving the clock structure through using one clock instead of the original four clock technology. cooperating the instruction work step, the new clock structure executed one clock cycle per instruction

    針對pic16c5x系列微控制器不能適用於高速場合的需要，對其時序結構進行了改進設計，用單時鐘代替原來的四相時鐘技術，採用二級流水結構，配合指令的工作節拍，使指令執行周期縮短為單個時鐘周期。
  19. This paper presents the yh ts - 1 instruction architecture, which based on the vector expansion of arm v4 instruction architecture. it supports vector processing and scalar processing in the same instruction set

    本文提出了基於armv4指令集體系結構擴展的銀河ts - 1指令集體系結構，在同一個指令集內同時支持標量機制和向量機制。
  20. The digital signal processor becomes the preferred utility for realizing digital arithmetic rapidly and precisely relying on its particular hardware and instruction architecture

    而dsp （數字信號處理器）以其特有的硬體體系結構和指令體系成為快速精確實現數字信號處理演算法的首選工具。
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