instruction cycle 中文意思是什麼

instruction cycle 解釋
指令周期
  • instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
  • cycle : n 1 循環，周期，一轉。2 周時，周年，年紀。3 （詩、故事等的）始末。4 自行車，三輪車，摩托車。5 【...
  1. Instruction fetch cycle

    取指令周期
  2. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  3. The processing required for a single instruction is called an instruction cycle

    處理一條指令的過程稱為指令周期。
  4. At the beginning of each instruction cycle, the cpu fetches an instruction from memory

    在每一個指令周期的開始， cpu從內存中取一條指令。
  5. Using the simplified two - step description explained above, the instruction cycle is depicted in figure 2 - 3

    以上述最簡單的兩個步驟為例，指令周期如圖2 - 3 。
  6. The design team s goal was to complete one instruction per clock cycle, and to accommodate 300 calls per minute

    設計小組的目標是在每個時鐘周期內完成一條指令，從而每分鐘可以處理300個電話。
  7. Id instruction decoder. this unit is capable of decoding up to 3 instructions per cycle

    命令解碼。本單元每循環能解三條指令。
  8. Based on analysis, we finished the architecture design and the division of the functional modules. allowing for the pic16c57 mcu can not suit the high speed situation, we improving the clock structure through using one clock instead of the original four clock technology. cooperating the instruction work step, the new clock structure executed one clock cycle per instruction

    針對pic16c5x系列微控制器不能適用於高速場合的需要，對其時序結構進行了改進設計，用單時鐘代替原來的四相時鐘技術，採用二級流水結構，配合指令的工作節拍，使指令執行周期縮短為單個時鐘周期。
  9. In other words, software interrupts always occur at the beginning of an instruction execution cycle

    換句話說，軟體中斷常常在指令運行周期的開始發生。
  10. The objectives of the workshop were to : expose participants to new trends on interactive radio instruction ( iri ) ; acquaint them with new skills and knowledge on iri methodology, scripting and project cycle management ; inculcate basic skills to enable participants facilitate, monitor and evaluate the project. ; create a forum for interaction amongst the implementers of the project and front line workers to evolve best approaches to be adopted to move the iri project forward, and to enhance the knowledge, skills and competencies of participants to strengthen their capacity to mobilise and sensitise pastoralists to support the iri project initiative in schools

    此次研討會有幾個目標：介紹有關互動式廣播教學的新趨勢；透過訓練，讓參與者熟悉該教學方法，教案的寫作及評估管理；灌輸有助於有效執行與評估教案的基本技能；在所有的參與者之間，包括執行該訓練計畫的人以及第一線的工作人員，創造一個能夠互動對話的空間，以引導出讓互動式廣播教學得以順利進行的最佳方式；以及，增加所有參與者的知識，技能與競爭力以強化他們動員牧民的能力，讓互動式教學能在學校順利展開。
  11. All the 32 registers are directly connected to the arithmetic logic unit ( alu ), allowing two independent registers to be accessed in one single instruction executed in one clock cycle

    所有的寄存器都直接與算邏單元（ alu ）相連接，使得一條指令可以在一個時鐘周期內同時訪問兩個獨立的寄存器。
  12. And some effective techniques are discussed to lower the clock period and cpi ( cycles per instruction ) of the pipeline. to eliminate the clock frequency limitation by some complex instructions " long executing time and achieve single - cycle throughput, a scalable super - pipelining extension technique together with a high performance / cost pipeline shift mechanism is presented in this paper

    為避免流水時鐘頻率受制於某些復雜運算指令較長的運算時間，又要達到單周期完成一條運算指令的吞吐量指標，本文提出對ex級進行可伸縮超流水擴展的思想，提出並實現了一種高性加比的切換控制方案。
  13. On the base of calculating customer value on each phrase of customer life cycle, investing and retaining strategies to customer relationship are proposed to provide instruction for enterprises " decision to reduce the relationship cost and to develop loyal customer

    從客戶生命周期角度在將客戶價值細分的基礎上，提出了企業客戶關系投入及客戶保持策略，力圖節約成本並培養忠誠客戶，旨在為企業經營決策提供指導。
  14. One of the key elements to achieving higher performance in microprocessors is executing more instructions per cycle. however, dependencies among instructions, varying latencies of certain instructions, and execution resources constraints, limit this parallelism considerably. in order to exploit instruction level parallelism, processor should employ data dependence analysis to identify independent instructions that can execute in parallel

    當前，在微處理器體系結構研究中，為了充分提高微處理器的處理性能，主要採用了指令級并行技術（ ilp ） ，指令級并行性的開發程度對發揮微處理器的硬體特性，提高程序運行性能至為關鍵。
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