ip core 中文意思是什麼

ip core 解釋
器知識
  • ip : 1. initial point 起點。2. Internet Protocol 【計算機】網際協議。
  • core : CORE ＝Congress of Racial Equality 〈美國〉爭取種族平等大會。n 1 果心。2 （事物、問題等的）中心，...
  1. 6. the methodology of designing the eight - bit cisc microprocessor ip core is discussed

    討論了八位cisc微處理器ip核的設計方法。
  2. Design and implement transaction level character describer and transaction level ip core ’ s data management, transaction level ip core makes up of ip description cell, ip description schema and ip description schema aggregation, ip description cell is the smallest unit composing ip data - base, ip description schema makes up of many ip description cells, ip description schema aggregation makes up of many ip description schemas. ip description schema aggregation integrallty defines ip core ’ s data structure in the ip data - base

    設計實現了事務級特徵描述以及事務級ip核的數據管理，事務級ip核由ip特徵描述單元、 ip特徵描述符、 ip特徵描述集合構成， ip特徵描述單元是構成ip庫的最小單位， ip特徵描述符由若干ip描述單元構成， ip特徵集合由ip特徵描述符構成， ip特徵描述集合完整的定義了一個ip核在ip庫中存放的數據結構。
  3. At last the algorithm of ddmf is achieved by the investigation tool of altera company ? quartus ii and the vhdl language, and its ip core is also achieved which is used not only in the satellite navigation position system, but also in the long pn code dsss system. ddmf investigated in the dissertation gives a good way to design the rapid pn code acquisition in the beidou project, and the technology has the definite theory and practice significance

    此外還應用altera公司的最新的fpga開發工具quartusiiv5 . 1 ，採用了國際標準的硬體描述語言? vhdl語言，對數字差動匹配濾波器和傳統匹配濾波器演算法予以實現，開發了該演算法的軟ip核，可以對所應用的擴頻碼長度， a / d采樣后的數據量化階數，所用擴頻碼等可進行隨意改寫。
  4. High precision ad chip is used for intermediate frequency data sampling and fpga of virtex - series is used for the implementation of intermediate - frequency orthogonal system, which includes the sequencing control design for mult - channel radar system with verilog, the application of ip core of digital filter and fifo, as well as the communication control module with dsp. as the master control part, the software programming for the communication between dsp and fpga is designed. the experimental result with hardware circuit shows the design is valid and practical

    採用高精度的adc晶元完成中頻采樣，通過virtex -系列fpga設計中頻正交系統，主要包括通過verilog語言實現多路雷達中頻接收的時序控制，通過濾波器ip核實現濾波器的設計，以及利用c語言實現dsp的通訊控製程序設計。並給出了fpga在資源和速度上一些優化的方法，調試過程中影響中頻正交接收性能測試的因素。
  5. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  6. There are lots of illustrations in this paper which make the system architecture, ip core structure and software flow easy to be understood

    本論文以大量的圖示形式介紹了系統中各部分的設計，使得系統架構、 ip核結構和軟體流程等一目了然，淺顯易懂。
  7. The ip core is made up of four modules, which are alu _ module, control _ module, timer _ module and port _ module

    這個ip模型主要由運算器模塊，控制器模塊，時鐘模塊和埠模塊四個部分組成。
  8. Design the data path of the risc 51 ip core. emphasis on the arithmetic logical unit ; 3. design the control path of the risc 51 ip core to make the risc 51 ip core ' s instruction set compatible with mcs51 microcontroller ; 4

    （ 3 ）設計risc51ipcore控制通路，實現risc51ipcore內部指令與原mcs51指令系統的完全兼容，具體設計原mcs51指令與risc結構51核指令的轉換過程，及正確的指令時序。
  9. This design is the first solid - state memory system for satellite, which can confront with multi - clock sources and multi - data sources compatibly. it is the fist design that integrates all functions of data processing and control into a single programed logic device. this design can be an ip core that can bring large advantage when system upgrade in the future

    本星載固存系統是我國星載固存系統中第一個採用多數據源，多時鐘源進行兼容設計的單一固存系統；第一個採用ip化、參數化設計思想，採用單一邏輯編程器件做為固存系統唯一控制部件，為以後系統升級帶來了很大好處；第一個採用功耗均衡思想來降低系統功耗。
  10. The design of ip core is the most practically useful and referential for developing and perfecting ip core store in our country. moreover, the ip soft core has a large economic market

    此ip軟核的開發，對於我國開發和完善擁有自主知識產權的ip核庫有著重要的實用價值和借鑒意義。
  11. The ip core contains a successive approximation adc and interface control circuit

    該ip核由逐次逼近型模數轉換器以及控制介面電路所構成。
  12. High implementation costs has pushed open hardware engineers to move to the ip core design on programmable logic devices, because designs for the devices are more malleable, and the devices themselves are more easily modified

    高實現成本已經促使開放硬體設計人員轉向可編程邏輯設備上的ip內核設計，因為設備設計更具延展性，並且設備本身更易修改。
  13. Secondly, the periphral controller ip core is realized

    然後具體實現了該外圍控制晶元。
  14. 6 ip design flow in the process of building ip library is researched in this dissertation. design flow and methodology of ip core - - 8 bit risc micro - controller soft ip core ( hgd08r01 ) and the demonstration of hgd08r01 soft ip core complying with vsia standard is gi

    6 、研究了ip庫建設中的ip設計流程，並具體研究芯核類ip ?一八位risc二微控制器ip軟核（ hgd08r01 ）的設計流程和設計方法，並依據vsia標準對2 hgd08r01ip軟核實施了標準化工作。
  15. This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design

    本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。
  16. With the ip core of ieee - 488. 2 protocol and the next research, we can make control chip of ourselves " and use it in the interface card of internat - gpib and usb - gpib

    有了ieee - 488協議的ip核，再加上以後繼續深入的研發，能夠實現測控領域gpib介面控制晶元的自主化，並能夠靈活應用在以太網? gpib 、 usb ? gpib各種介面卡中。
  17. We are developing advanced ip core of system lsi for digital av application, such as a video codec and an audio codec, with high performance, high quality, small size and low power consumption

    我們正從事數字影音產品先進ip核的開發，例如高性能、高質量、小尺寸和低功耗的視頻編解碼器和音頻編解碼器。
  18. This thesis introduces usb2. 0 device controller ip core for fpga designs

    本文主要研究usb2 . 0設備控制器的ip核設計。
  19. In conclusion, the usb2. 0 device controller ip core is verified under pc ' s plug and play

    本文所設計的usb2 . 0設備控制器ip核能做到在pc機上熱插拔。
  20. The bus is programable. at this rate the user can program the mcu firmware to configure the correlative registers before using the bus. the user can also change the bus channel in the gpmb when the data of different type is to be transfered. in conclusion, gpmb module provides the communication channel between usb2. 0 ip core and peripheral

    它提供32位可編程介面，用戶可以通過usb2 . 0ip核中的mcu固件對內部相關寄存器進行配置來使用這32位總線，並可以在內部的多總線通道中切換，以達成usb2 . 0ip核對外圍介面的控制及數據傳輸，進而完成設備通過usb2 . 0介面ip核與主機通信的功能。
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