logic array 中文意思是什麼

logic array 解釋
邏輯排列
  • logic : n. 1. 邏輯，理論學。2. 推理[方法]；邏輯性，條理性。3. 威力，壓力，強制（力）。
  • array : vt 1 打扮，裝飾。2 使…列隊，排列。3 提出（陪審官）名單，使（陪審官）列席，召集（陪審官）。n 1 整...
  1. The main work included : the classical lambda calculus was modified to describe the character of dynamic fuzzy ; the abstract syntax of dfl programming language was described through bnf notation ; an operational semantics model of dfl programming language was proposed with a ternary array < dfsc, dfo, dfss > and then some basic data types and several mechanisms of constructing new data types were defined ; the frame of dfl progaramming language was provided ; it was described how to solve some problems applying the operational semantics model ; the correctness and reliability of the operational semantics model were proved by hoare logic and denotational semantics

    主要內容包括:變形傳統的演算，以更好地描述具有動態模糊性的問題;通過bnf描述了dfl程序設計語言的抽象語法;通過一個三元組< dfsc ， dfo ， dfss >給出了dfl程序設計語言的操作語義模型;給出了dfl程序設計語言的基本框架結構;給出了該操作語義模型的一些應用實例;通過hoare邏輯和基本指稱語義對本文所定義的操作語義模型的正確性和可靠性進行了證明。由此可見，本文從全新的角度定義了一種可以處理動態模糊問題的程序設計語言。
  2. In computers, a logic network in the form of an array of input leads andoutput leads with logic elements connected at some of their intersections

    在計算機中，由輸入線和輸出線陣列形成的一種邏輯網路，在它們的某些交叉點上用邏輯元件相連接。
  3. In computers, a logic network in the form of an array of input leads and output leads with logic elements connected at some of their intersections

    在計算機中，由輸入線和輸出線陣列形成的一種邏輯網路，在它們的某些交叉點上用邏輯元件相連接。
  4. In the synchronous " model, based on the idea of polygonal flux linkage locus, by means of constructing the switch state period table of three phrase voltage inverter is required. in the brushless model, the igbt ( isolated gate bipolar transistor ) switch state period table is gained by gal ( generic array logic ) which analyzes the signal of position feed - back

    在同步方式下，基於多邊形磁鏈軌跡法的思想，用作圖法求得三相電壓型逆變器的pwm波形序列；在無刷直流方式下，用gal對位置反饋信號進行邏輯綜合，得到開關管的導通規律。
  5. With the quickly development of field programmable gate array, fpga with more than million logic gates has been used

    隨著fpga （現場可編程門陣列）技術的快速發展，萬門以上乃至幾十萬門邏輯陣列的使用越來越普遍。
  6. An application exception represents the occurrence of a business logic error : withdrawing more than an account balance, reserving a seat which is already reserved, getting a credit card charge denied, etc. this is different from a system exception, which represents a system level error like running out of memory or running past the end of an array

    應用程序異常表示發生了業務邏輯錯誤：取款超出了賬單余額、預訂已被訂出的座位、獲取已被凍結的信用卡的費用等等。這同系統異常不同，系統異常表示系統級別的錯誤，如耗盡內存或者數組越界。
  7. The article all so try to look out the problems in the fables system of the chinese teaching material, and try to investigate and research the problem, all this based on thinking of the characteristic of chinese teaching, the characteristic of the times, the logic array of the knowledge and the developing regulation of the students, and so on

    本文通過對語文教材選用寓言的必要性、可行性進行分析，認識寓言對教材建設、教師教學、學生學習的重要意義，並綜合考慮時代的特點、知識邏輯序列、語文學科的特性、學生身心發展規律等諸多因素，嘗試對現行語文教材中寓言體系所存問題進行調適研究。
  8. Computing minimal hitting sets with logic array in model - based diagnosis

    基於模型診斷中用邏輯數組計算最小碰集
  9. Logic array network

    邏輯數組網路
  10. A magnetic processor constitutes an array of logic gates, each of them programmable individually by the software

    磁處理器由邏輯閘陣列所組成，其中每個閘都可以由軟體獨立編程。
  11. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory. in 1995, barenco showed that almost any two - bit gate is universal, so building a feasible two - bit logic gate is the first step to engineer a quantum computer. in principle, the quantum bit can be carried by any two states system

    在眾多的量子計算機模型中目前討論最廣泛的是量子計算機門組網路模型，量子計算機門組網路模型是經典計算機門組網路結構的量子推廣，它是根基於barenco等人所證明的「一個兩比特受控操作和對單比特進行任意操作的門可以構成一個『通用量子邏輯門組』 」之上的。
  12. Cracking a data encryption and decryption system using multi - valued logic array

    對一種基於多值邏輯陣列變換的加解密系統的破解
  13. Programmable logic array

    可編程序邏輯陣列
  14. Researched the methods to test configrable logic block ( clb ) and its sub - blocks. based on a “ divide and conquer ” methodology, the clb resources are divided into three basic blocks : logic units, carry logic module ( clm ) and lut ’ s ( look up tables ) ram - mode. the testing configurations are implemented based on a two - dimensional array structure for logic blocks

    主要基於「分治法」對clb及其子模塊進位邏輯（ clm ） 、查找表（ lut ）的ram工作模式等進行了測試劃分，分別實現了以「一維陣列」為基礎的測試配置和測試向量，以較少了測試編程次數完成了所有clb資源的測試。
  15. Gal : generic array logic

    通用陣列邏輯
  16. Cellular logic array

    細胞邏輯陣列
  17. To realize the real - time tracking image target, we use the cpld ( c ' omplex programmable logic device ) to control the system logic and use ipga ( field programmable gate array ) to preprocessing the image

    為了滿足系統的實時性要求，運用大規模可編程邏輯陣列cpld進行邏輯控制和現場可編程門陣列fpga對採集的視頻圖像做預處理。
  18. Pal : programmable array logic

    可編程陣列邏輯
  19. Cmos image sensor consists of image array logic registers, memory, timer pulse generator and converter

    Cmos圖像傳感器包括圖像陣列邏輯寄存器、存儲器、定時脈沖發生器和轉換器在內的全部系統。
  20. Combined with listless spiht ( set partition in hierarchical trees ), a remote sensing image compression hardware system using fpga ( field programmable logic array ) technology is implemented on virtex chip

    在使用fpga技術的基礎上，一種結合無鏈表spiht的遙感圖像壓縮演算法在可編程器件virtex晶元上得到了實現。
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