low-power logic 中文意思是什麼

low-power logic 解釋
低功率邏輯, 低功耗邏輯
  • low : adj 1 低的；淺的，矮的。 low flight 低飛。 a low temperature 低溫。 low tide [water] 低潮。 The g...
  • power : n 1 力，力量；能力；體力，精力；（生理）機能；〈常 pl 〉才能。2 勢力，權力，權限；威力；政權；權...
  • logic : n. 1. 邏輯，理論學。2. 推理[方法]；邏輯性，條理性。3. 威力，壓力，強制（力）。
  1. This dissertation detailedly investigate the symbolic logic and some typical techniques for low power fsm logic synthesis and optimization

    論文詳細討論了低功耗有限狀態機綜合與優化中的符號邏輯和一些典型方法。
  2. Based on many other circuit formats, a new kind of logic - level circuit representation, called unified middle - level circuit format ( umcf ), is defined in this paper, in which some special operations on circuit related with power estimation and low power design. umcf can not only interchange circuits of different formats, but also convert circuits to hspice acceptable files, which can be used for transistor level power estimation

    本文結合多種不同的電路格式，自主定義了一種邏輯級電路的中間表示形式（稱為umcf ）和一系列極具特色的與低功耗技術相關的操作，它不但可以實現與其他多種電路格式之間的相互轉換，還可以將電路直接轉換成hspice可以接受的文件，進行晶體管級的電路功耗估計，這樣可以在公認的高精度的功耗模擬器上，對本文的結果進行有效的驗證。
  3. According to elaborate analysis of clock logic in general purpose processor, we apply multi - bit clock gated flip - flops design to reduce the power of registers and clock trees concurrently, so the power of the clock network in processors can be drastically reduced. 3. a low power issue queue architecture is proposed

    一方面利用帶門控使能的觸發器電路降低時鐘節點的平均翻轉，另一方面通過多比特觸發器的採用進一步降低了時鐘樹規模，從而在不增加asic物理設計復雜度的情況下大大降低了龍芯處理器的時鐘網路功耗; 3 .提出了亂序多發射隊列的低功耗結構。
  4. In addition to the dram array, the logic circuitry with the body - bias - controlled soi transistors has been developed for high - speed operation. combine some new techniques for power reduction and our dram array, we design a new low - power soi cmos dram structure and study the performance of our circuits. the results we got in the simulation and test are valuable

    第三種，為了簡化soi材料的電學性能測試結構，使它的測試，分析，計算摘要與傳統的mos模型相兼容，我們通過引入一個耦合因子，將傳統的mos模型的測試方法，公式引入soi材料的c v ， i刁測試過程。
  5. Abstract : this paper analyses the source of power, the advantage and disadvantage of some low - power logic styles, and how to decrease the power on voltage and clock

    文摘:分析了功耗的產生原因和幾種不同的低功耗電路結構的優缺點。論述了如何從電源設計、時鐘管理等方面降低功耗。
  6. At the logic synthesis stage, we make some research on the principles of logic synthesis at first, then by utilizing tsmc0. 25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2. 25v, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15. 3ns and the chip area is 0. 395mm2

    在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然後利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，採用與模擬時相同的時鐘，關鍵路徑為15 . 3ns ，晶元面積為0 . 395mm ~ 2 。
  7. Maverick ? ep7312 processor is designed for high - performance ultra - low - power system on chip application, enables flexible interface devices, such as led conroler, touch screen, spi, usb. the core - logic functionality of the cpu is built around an arm720t processor

    它包含arm7tdmi處理器內核和豐富的外圍介面，支持dram存儲器，具有lcd顯示、觸摸屏、 spi利usb介面等功能介面模塊。
  8. Low power vlsi designs can be achieved at various design levels, which rang from circuit, logic, architecture and algorithmic ( behavioral ) levels to system level, according to the down - top design flow

    超大規模集成電路低功耗設計可以在不同的設計層次進行考慮，自下而上分可以分為：物理層、邏輯層、結構層、演算法（行為）層和系統層。
  9. The focus of our research in the low - power design of viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment

    從這里發掘功耗的潛力是很大的，主要通過優化演算法、優化邏輯結構來實現。
  10. In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter

    在電路模塊分析中，重點介紹了語音的輸入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等，並且給出了在硬體電路設計和調試過程中的問題與解決辦法。
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