memory controller 中文意思是什麼
memory controller
解釋
存儲控制器- memory : n. 1. 記憶；記憶力；【自動化】存儲器；信息存儲方式；存儲量。2. 回憶。3. 紀念。4. 死後的名聲，遺芳。5. 追想得起的年限[范圍]。
- controller : n 1 管理人，主管人。2 （會計的）主計人，檢查員；〈英國〉（特指宮廷、海軍等的）出納官〈常作 comptr...
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Crossbar - based memory controller
交叉內存控制器 -
In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical
在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。 -
The hardware of the monitoring system mainly consists of the dsp controller, nonvolatile memory, led, clock management, keyboard interface, sci communication units and can communication units
系統的硬體部分主要包括了dsp微處理器的基本外圍電路、非易失性存儲、 led顯示、時鐘管理、鍵盤介面，以及sci通信和can通信等單元電路。 -
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
In the abb system, microprocessor msp430f437ipz was the main controller. and ferroelectric random access memory fm24c04 was adopted to store the most important real - time data
鐵電存儲器的技術，保障了汽車黑匣子在嚴重事故中仍能保持實時數據的完好，使得系統的可靠性和安全性都得到很大的提高。 -
Controller, bubble memory
磁泡記憶控制器 -
The controller getting off shift, for example, can recount from episodic memory the aircraft involved and the series of control actions taken for any troublesome situation that occurred
例如，管制員離開崗位后，仍然能從經歷性記憶中敘述出那些曾發生的困難的情況下所做出的一系列管制行為和有關的航空器。 -
From the point of view of the device, say the floppy disk controller, it will see only the address space that its control registers are in ( isa ), and not the system memory
從設備的角度來看，比如說軟盤控制器，它只能看到在isa總線上的控制寄存器而不是系統內存。 -
This system ' s hardware adopts dsp - embedded controller, which can process digital signal independently. the controller communicates with pc by accessing memory. on the side of controller, c language is used to write the interpolation program and the interruption service program, while on the side of pc, visual c + + is used to write programs in which functions of editing nc - code, real - time control and human - machine interaction interface is fulfilled
該數控系統的硬體採用了具有獨立數字信號處理功能的dsp型運動控制器，控制器通過內存訪問與pc機通信，使用c語言編寫了控制器端的中斷服務和插補程序，使用visualc + +編寫了pc端的數控代碼編輯、實時控制和人機交互界面程序。 -
The five main sections of this thesis are as follows : 1 ) component parts and working flow of intelligent community 2 ) hit communicating protocol 3 ) technical points of hardware design single chip micro - controller touch screen rf data transmitting identification confirmation flash memory 4 ) software design under avr studio3. 53 ide 5 ) method and result of system test
論文包括以下幾個主要部分： 1 ）智能小區系統組成及系統運行流程2 ） hit通信協議3 ） hit - 5終端硬體電路設計單片機技術觸摸屏輸入技術無線數據收發技術身份識別技術flash存儲技術4 ） avrstudio3 . 53程序設計5 ）系統測試方法及調試結果 -
Options include stand - alone printer controller, rotary cutter, and expandable flash memory cartridges
Ttp - 342m工業條碼印表機工業級鐵殼設計， 300dpi -
An apparatus and method having a de - interleaving memory and a controller is used for de - interleaving interleaved data in a coded orthogonal frequency division multiplexing receiver
正交編碼分頻多工接收器中一種具有一反交錯記憶體和一控制器，而用來將已交錯資料反交錯的裝置與方法。 -
The fpga of xilinx inc. works as a important part, with which many functional modules, including a controller of lcd display, a fifo ( first in first out ) memory, a controller of sampling clock, and so on, were implemented
Xilinx公司的fpga （現場可編程門陣列）作為系統的外圍控制器，實現系統的其他很多功能模塊，包括lcd （液晶顯示）控制器、測頻和測周模塊、 fifo （先進現出存儲器） 、采樣時鐘控制器，等等。 -
Technical points of hardware design single chip micro - controller dtmf / fsk code & decode flash memory ps / 2 serial port interface rs - 232c serial interface 4
硬體電路設計單片機技術dtmf fsk編解碼技術flash技術ps 2串列口技術rs - 232c串列通訊介面技術4 -
The results of the hdl simulation and fpga verification showed that image enhancement improved greatly the image quality. cooperating with software a circuit that can read and write flash memory and a remote controller hardware decoder were also designed in this thesis. after hdl
本文還設計了與軟體配合能讀、寫閃存的電路以及紅外遙控的硬體解碼電路，經hdl模擬及fpga驗證，所設計的兩種電路能完全滿足晶元商用要求。 -
Since then, jeilin has developed many important core technologies such as jpeg codec, usb device controller, high - performance image processor, dsc controller, memory card interface controller, ide interface controller, tv encoder, and mpeg - 4 codec, etc. with these core technologies, jeilin has successfully promoted cost - effective solutions for customer s products such as pc camera, web camera, dsc, photo card reader and digital picture frame
傑霖科技致力於影像與多媒體ic的設計與研發，已成功開發多種pc周邊控制晶片多媒體影音控制晶片及客戶委託之應用ic如通訊產品asic等研發。針對影像處理技術， jpeg codec壓縮及解壓縮技術mpeg 4 codec系統整合tv encoder介面技術usb 2 . 0介面技術及ide介面技術，皆有豐富的開發與整合的成功經驗，並極力推陳出新。 -
Based on s698 technology, obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller, etc. the bus interfaces is composed of i2c spi magnetic card interface and ic card interface. obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition
Obt - devsys - s698是s698系列嵌入式處理器開發板中的一員，其上包括：具有32 64 - bit浮點運算單元的32 - bit嵌入式處理器，主頻160mhz ， sram存儲器， flash存儲器具有三路uart介面，一路ps 2介面， led發光二極體控制電路，中斷操作按鈕其外擴總線包括i2c總線介面spi總線介面磁卡介面智能卡介面等。 -
Memory controller design and ip interconnection are the common issues in system - on - a - chip ( soc ) design. having analyzed the established ip interconnection strategy and sgram characteristics, the author put forward the multi - agent momery interface interconnection strategy, defmed the interface protocol and implemented the momery interface design using finite state machines
存儲器控制電路的設計和ip互連是soc設計中常遇到的問題。在分析了已有的ip互連機制和sgram特性后，本文給出多客戶存儲器介面的互連策略、定義了介面通信協議並且用狀態機實現了該介面電路的設計。 -
Gmch graphics memory controller hub
圖形和內存控制中心 -
I guess the most notable thing is putting the memory controller on the cpu chip, which has already been done by the alpha people, and has already been shown to have upsides and downsides
我想最值得注意的就是將存儲器控制器放到cpu晶元上，這一點開發alpha的人員已經使用了，而且已經表現出有利也有弊。
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