memory data bus 中文意思是什麼
memory data bus
解釋
存儲器數據總線-
The microprocessor uses the address bus to locate data stored in memory.
微處理機使用地址總線設定在存貯器中存貯的數據的地址。 -
There will be a separate data bus connecting the central processing unit to memory devices.
有一條獨立的數據總線將中央處理機與存儲器連接起來。 -
This high - speed data acquisition card designed is based on pci bus and have high capacity memory interface. it combines high - speed date acquisition and high capacity real - time memory
為此，本文設計了一款基於pci總線且具備可擴展大容量存儲設備介面的高速模擬信號採集卡，將高速數據採集和大容量實時存儲結合在一起。 -
The fourth chapter : in this chapter, it introduces the hardware designing of the dsp system based on pci bus and states every module of the hardware designing : circuit of signal adjusting, filter circuit of anti - overlap, circuit of data - acquisition automatically, expanding circuit of dsp memory, circuit of voltage matching, interfaces circuit of pci etc. it also includes theoretic basis and procedure of pcb designing
第四章介紹基於pci總線的dsp系統硬體設計。敘述了硬體設計的各個模塊：信號調理電路、抗混疊濾波電路、自動數據採集電路、 dsp存儲器擴展電路、電平匹配電路、 pci介面電路等，以及pcb設計的理論基礎和設計過程，並給出了設計和調試的結果。 -
There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way
Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。 -
This software system of chip simulation ' s main function is simulate the main logic circue chips, 8088cpu, memory, registers, data _ bus, address _ bus, control _ bus and other chips. this function is based on the object - oriented technology, construct the chip object by the chip classes that we defined. because this system need to simulate the detail function of computer hardware, so this system simulate the 8088cpu ' s order system, support the basic compile languages. one of the feture of this system is the simulation of a static memory, the room of the memory can be configured by testers from 1k to 64k
由於本系統在模擬過程中需要完全模擬計算機硬體的工作原理，因此本系統還模擬了8088cpu的基本指令系統，支持基本的匯編指令，在實驗過程中可以由實驗者輸入相應的匯編指令以執行操作，並查看各晶元器件的引腳參數變化情況。本系統模擬的一個特點是動態模擬了存儲器的大小，存儲器容量可以由實驗者根據需要自己設置，范圍從1k到64k 。 -
The product has the following characters : all - purpose input, completed separated signal channels, collection of the signal data by scanning, the display technique of lcd big screen, flash memory ; capacious compatible floppy disk, 36 types of signals, multiple alarms, communication of rs232 / 485 and hart confered - link with a view to second generation technique of the field - bus. during the developing course, i used the method of reliability design to design hardware, and researched carefully the process of weak signal. pass to practice, the product has achieved all aim of the design
系統在功能上實現了萬能輸入，信號通道之間的完全隔離，信號的掃描採集，大屏幕lcd顯示技術， flash存儲器進行數據存儲，大容量的具有兼容性的電子軟盤， 36種信號方式，多種報警方式， rs232 / 485通訊，以及著眼于下一代的現場總線技術的hart協議介面等。 -
The dissertation implements acquisition data high speed transfer with pci bus dma technology and designs four group high speed streaming disk interface to expand high speed and high capacity memory and implement mass storage
本文運用基於pci總線的dma技術實現了採集數據的高速傳輸，並通過設計4組高速流盤介面來外擴高速超大容量存儲器，實現了連續採集的海量存儲。 -
3. with time series simulation software, the cpu ’ s i / o ports simulate i2c bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices
3 、採用軟體模擬時序使cpu的i / o口模擬i2c總線，實現了單片機與時鐘晶元、溫濕度傳感器、存儲晶元等器件的數據交換。 -
Peripheral devices in embedded systems are often connected to the mcu as memory - mapped i / o devices, using the microcontroller ' s parallel address and data bus. this results in lots of wiring on the pcb ' s to route the address and data lines, not to mention a number of address decoders and glue logic to connect everything
由於并行總線擴展時連線過多，外圍器件工作方式各異，外圍器件與數據存儲器混合編址等，都給單片機應用系統設計帶來布線復雜，線路板面積大，易引起emi和esd干擾等困難，這在一些比較復雜的應用系統是難以接受的。 -
In smp also known as " tightly coupled " multiprocessing and a " shared everything " system, processors share memory and the i o bus or data path, and a single copy of the operating system controls the processors
在smp （也稱為「緊耦合的（ tightly coupled ） 」多處理和「共享所有」的系統）中，處理器共享內存和i / o總線或者數據通路，由單一的操作系統來控制這些處理器。 -
In the dissertation ， we discribe the implementation of large capability video data acquisition system based on pci bus of computer 。 the system is composed of data acquisiton card and corresponding software 。 the data acquisiton card include two acquisition channels ， 8 - bit digitization at rates up to 13. 5mhz 。 frist ， the architecture of the video data acqusition system is studied 。 then ， the function and implementation methode of each module are introduced in detail 。 the control module of the video data acqusition card is implemented by using of the isp technology of cpld and vhdl programming technology 。 the a / d converter used assembler to implement the initialazation programe 。 and the double buffer technology is used for large capability data acqusition. because a contiously large memory is difficult to apply in windows operating system 。 finally we use broland c + + to introduced the devleoping procedure of drivers 。
在實際的研製過程中，利用cpld的在系統可編程（ isp ）技術和基於vhdl語言的可編程邏輯器件設計技術實現了視頻數據採集卡的控制模塊。在視頻的a / d轉換模塊，用匯編程序模擬i2c總線對初始化a / d轉換晶元。針對大容量數據採集，採用了雙緩沖技術解決wndows操作系統下難以申請到大容童連續內存的間題。 -
A memory address consists of binary data being output on an appropriate bus which we call the address bus.
一個存儲器地址是由輸出到適宜的總線上的二進制數據所組成。這個總線我們稱為地址總線。 -
The task of realtime display on lcd and the complicated control arithmetic are implemented in this smps system, and a microcontroller with high resolution, high speed, high integration, large memory is necessary. in this paper, the design theory of s / h ware module which forms the smps control module and the design scheme is discussed in detail. in this system, the digital compute - control module is implemented with samsung ’ s high resolution, high integration, arm core microcontroller s3c44b0 and ad converter with 16bit resolution produced by ad company, ad7705. the ad7705 implements the data acquisition of the voltage and current feedback signal, and transfer the data to microcontroller through spi bus, which is implemented with s3c44b0 ’ s gpio, for computation and display
本開關電源系統不僅完成lcd的實時顯示，還要完成復雜控制演算法，需要高速度、高精度、高集成度、大存儲空間的微控制器的支持。本文詳細的論述了構成電源控制模塊的各個軟硬體模塊的設計原理和設計方案。本系統提出了以samsung公司的高速度、高集成度的基於arm架構的微控制器s3c44b0與ad公司具有16位解析度的模數轉換器ad7705晶元構成數字採集運算控制模塊。 -
And a faster processor is useless unless the memory and bus architecture allows pcs to deliver data to the processor more efficiently
除非存儲器和總線的體系結構使pc機能更有效地向處理器輸送數據，否則速度更快的處理器也沒有用。 -
Transfer all of your data over the bus, even when using deep memory
即使在使用深存儲器時，也能傳輸所有數據 -
For example, for intel - based isa bus computers, this information indicates whether it is a memory - parity error or a bus - data error
例如，對于基於intelisa總線的計算機，此信息會指出是否是內存奇偶校驗錯或總線數據錯誤。 -
Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology
然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。 -
Though the analysis about the powerpc bus, there are four parts in biu : instruction pretreatment part, address bus treatment part, data bus treatment part and data pos - treatment part. the second part focuses on the memory consistency
通過對powerpc結構的總線協議的分析，總線介面部分主要由指令預處理部分、地址總線處理部分、數據總線處理部分和數據后處理部分組成，完成微處理器和外部總線的數據交互。
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